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21(+1) channel high-density e1 line interface unit idt82p2521 version 1 december 7, 2005 6024 silver creek valley r oad, san jose, california 95138 telephone: 1-800-345-7015 or 408-284-8200? twx: 910-338-2070 ? fax: 408-284-2775 printed in u.s.a. ? 2005 integrated device technology, inc.
disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best pos- sible product. idt does not assume any res ponsibility for use of any circuitry described other than the circuitry embodied in a n idt product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent, pat ent rights or other rights, of integrated device technology, inc. life support policy integrated device technology's products ar e not authorized for use as critical com ponents in life support devices or systems un less a specific written agr eement pertaining to such intended use is exe- cuted between the manufacture r and an officer of idt. 1. life support devices or systems are devices or systems whic h (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose fa ilure to perform can be reasonably expecte d to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness.
table of contents 3 december 7, 2005 table of contents .......... ................ ................. ................ ................. ................ ................. ................ ................. ............. 3 list of tables .............. ................ ................. ................ ................. ................. ............... .................. ........... ............ ........... 7 list of figures ............. ................ ................. ................ ................. ................. ............... .................. ........... ............ ........... 8 features ............. ................. ................ ................. .............. .............. .............. .............. .............. ............... .............. ........... 10 applications........... ................ ................. .............. .............. .............. ............... .............. .............. .............. .............. ......... 11 description............. ................ ................. .............. .............. .............. ............... ............. .................... ........... ............ ......... 11 block diagram .................. ................ ................. ................ ................. ................ .............. ................. ................ .............. 12 1 pin assignment ....... ................ ................. .............. .............. .............. ............... .............. ................ ................. .......... 13 2 pin description ........... ................ ................. ................ ................. ................ ................. ................ ................. .......... 18 3 functional description ............... ................ ................. .............. .............. .............. ............. ............. ............ ........ 29 3.1 receive path ............. ................. ................ ................. ................ ................. ............... ................ .............. .......... 29 3.1.1 rx termination ......... ................. ................ ................. ................. ................ ............... ............. ............ ........ 29 3.1.1.1 receive differential mode ....... ................. .............. .............. .............. .............. .............. ............. 29 3.1.1.2 receive single ended mode .................... ................ ................. .............. .............. ............. ......... 31 3.1.2 equalizer ......... ................ ................. .............. .............. ............... .............. ............. ............. .............. .......... 32 3.1.2.1 line monitor ......... ................. ................ ................. ................ ................. ............... ............. ........ 32 3.1.2.2 receive sensitivity .. ................ ................. ................ ................. ................ ................ .................. 32 3.1.3 slicer ............. ................ ................. .............. .............. .............. .............. ............. ................ .............. .......... 33 3.1.4 rx clock & data recovery ....... ................ ................. .............. .............. .............. ............... .............. .......... 33 3.1.5 decoder .......... ................ ................. .............. .............. ............... .............. .............. .............. .............. ........ 33 3.1.6 receive system interfac e ................ ................. ................ ................. ................ ............... ................ .......... 33 3.1.7 receiver power down .... ................. ................. ................ ................. ................ ............... ................ .......... 34 3.2 transmit path ...... ................ ................. ................ .............. ............... .............. ............ .............. ................ ........ 34 3.2.1 transmit system interface ........ ................ ................. .............. .............. .............. ............. ................ .......... 34 3.2.2 tx clock recovery ............... ................. ................ .............. ............... .............. ............. ................. ............. 35 3.2.3 encoder ........... ................ ................. .............. .............. ............... .............. ............. ............. .............. .......... 35 3.2.4 waveform shaper ......... ................. ................ ................. ................ ................. .............. ................ ............. 35 3.2.4.1 preset waveform templa te .............. ................ ................. ................ ................. ............... ......... 35 3.2.4.2 user-programmable arbi trary waveform ............... .............. .............. .............. .............. ............ . 36 3.2.5 line driver ....... ................ ................. .............. .............. ............... .............. ............. ............. .............. .......... 38 3.2.5.1 transmit over current protecti on ................ ............... .............. .............. .............. .............. ........ 38 3.2.6 tx termination ......... ................. ................ ................. ................. ................ ............... ............. ............ ........ 38 3.2.6.1 transmit different ial mode ................ ................ ................. ................ .............. .............. ............. 38 3.2.6.2 transmit single en ded mode ................ ................. ................ ................. .............. ............. ......... 39 3.2.7 transmitter power down .......... ................ ................. .............. .............. .............. .............. ............... .......... 40 3.2.8 output high-z on ttip and tring ... ................. .............. .............. .............. ............... ............. .................. 40 3.3 jitter attenuator (rja & tja) .............. ................. ................ ................. ................ .............. ............... .......... 41 3.4 diagnostic facilities .... ................. ................ ................. ................. ................ ............... ............. ............ ........ 42 table of contents
idt82p2521 21(+1) channel high-density e1 line interface unit table of contents 4 december 7, 2005 3.4.1 bipolar violation (b pv) / code violatio n (cv) detection and bpv in sertion ............ .............. ............ ........ 4 2 3.4.1.1 bipolar violation (bpv) / code violat ion (cv) detection ...... ................ ............... .............. .......... 42 3.4.1.2 bipolar violati on (bpv) insertion ....... ................ ................. ................ ................. ............. ........... 42 3.4.2 excessive zeroes (exz) de tection ........... ................. ................. ................ .............. .............. ............ ........ 42 3.4.3 loss of signal (los) detection .. ............... ................. .............. .............. .............. ............... .............. .......... 43 3.4.3.1 line los (llos) ..... ................ ................. ................ ................. ................ ................. ................. 43 3.4.3.2 system los (slos) ............. ................ ................. .............. .............. .............. .............. ............. 44 3.4.3.3 transmit los (tlos) ........... ................ ................. .............. .............. .............. .............. ............. 45 3.4.4 alarm indication si gnal (ais) detection and generati on .............. .............. .............. .............. ........... ......... 46 3.4.4.1 alarm indication signal (ais) detection .......... .............. .............. .............. .............. .............. ...... 46 3.4.4.2 (alarm indication signal ) ais generation .............. ................ ................. ................ ................ .... 46 3.4.5 prbs, qrss, arb and ib pattern generation and detection .............. .............. ............... ........... ............ . 47 3.4.5.1 pattern generation .. ................ ................. ................ ................. ................ ................. ................. 47 3.4.5.2 pattern detection .... ................ ................. ................ ................. ................ ................ .................. 48 3.4.6 error counter ......... ................. ................ ................. ................ ................. ................ .............. ............ ........ 49 3.4.6.1 automatic error counter updating ........... ................ ................. ................ .............. ............. ....... 49 3.4.6.2 manual error counter updating ............ ................. ................ ................. .............. .............. ........ 50 3.4.7 receive /transmit multiplex functi on (rmf / tmf) indication ................. ................ .............. ............... ..... 51 3.4.7.1 rmfn indication ...... ................ ................. ................ ................. ................ ................ .................. 51 3.4.7.2 tmfn indication ...... ................ ................. ................ ................. ................ ................ .................. 52 3.4.8 loopback .......... ................. ................ ............... .............. .............. .............. ............. ............. .............. ........ 53 3.4.8.1 analog loopback ........ ................. ................ ................. ................ ................. ............. ................ 53 3.4.8.2 remote loopback .......... ................ ................. ................ ................. .............. .............. ............... 54 3.4.8.3 digital loopback ...... ................ ................. ................ ................. ................ ............... ........... ........ 55 3.4.8.4 dual loopback ............ ................. ................ ................. ................ ............... ............. .................. 56 3.4.9 channel 0 monitoring .... ................. ................ ................. ................ ................. .............. ................ ............. 58 3.4.9.1 g.772 monitoring ....... ................ ................. ................. ................ ................. ............. .................. 58 3.4.9.2 jitter measurement (jm) ....... ................ ................. .............. .............. .............. .............. ............. 59 3.5 clock inputs and outputs ................. ................. ................ ................. ................ ................ ............... .......... 60 3.5.1 free running clock output s on clke1 ............. ................ ............... .............. .............. .............. ............... 60 3.5.2 clock outputs on refa/ref b ................. ................. ................. ................ .............. .............. ............ ........ 61 3.5.2.1 refa/refb in clock re covery mode ......... ................. ................ ................. .............. .............. . 61 3.5.2.2 frequency synthesizer for refa clock output ............ ................ ................. ................ ............. 6 1 3.5.2.3 free run mode for refa clock output ....... ................. ................ ................. .............. ............. .. 61 3.5.2.4 refa/refb driven by external cl ka/clkb input ............. ................ ............... .............. .......... 61 3.5.2.5 refa and refb in loss of signal (los) or loss of clock condition . ............... .............. .......... 61 3.5.3 mclk, master clock input ........ ................ ................. .............. .............. .............. .............. ............... .......... 65 3.5.4 xclk, internal reference clock in put .............. ................ .............. .............. ............... ............ ........... ........ 65 3.6 interrupt summary ......... ................ ................. ................ ................. ................ ............... ........... ............ ........ 66 4 miscellaneous ......... ................. ................ .............. ............... .............. .............. ............. ............... ................. .......... 68 4.1 reset ............... ................. ................. .............. .............. .............. .............. ............. ............. .............. ............ ........ 68 4.1.1 power-on reset ......... ................ ................. ................ ................. ................ ................ ................. ............. 69 4.1.2 hardware reset .......... ................ ................. ................ ................. ................ ............... ........... ............ ........ 69 4.1.3 global software reset .. ................. ................ ................. ................ ................. ............... ............... ............. 69 4.1.4 per-channel software reset ......... ................ .............. ............... .............. .............. ............. ............. .......... 69
idt82p2521 21(+1) channel high-density e1 line interface unit table of contents 5 december 7, 2005 4.2 microprocessor interface ............ ................ .............. ............... .............. .............. .............. .............. ........ 69 4.3 power up ........... ................ ................. .............. .............. .............. ............... .............. ................ ................. .......... 70 4.4 hitless protection switching (hps) summary .............. ................. ................ ................. ................. ..... 70 5 programming information ... ................ ................. ................ ................. ................ ................. ................ ............. 73 5.1 register map ........ ................ ................. .............. .............. .............. .............. .............. ............... .............. .......... 73 5.1.1 global register ........ ................. ................ ................. ................. ................ ............... ............. ............ ........ 73 5.1.2 per-channel register .................... ................ ................. ................ ................. ............... ............... ............. 74 5.2 register description ..... ................ ................. ................ ................. ................ ................ ................. ............. 77 5.2.1 global register ........ ................. ................ ................. ................. ................ ............... ............. ............ ........ 77 5.2.2 per-channel register .................... ................ ................. ................ ................. ............... ............... ............. 85 6 jtag ........... ................. ................ ................. ................ ................. .............. ............. ............. .............. .............. ........... 117 6.1 jtag instruction register (ir) .... ................. ................ ............... .............. .............. ............. ............. ........ 117 6.2 jtag data register ....... ................. ................ ................. ................. ................ ............... ........... ............ ........ 117 6.2.1 device identification regi ster (idr) .......... ................. ................. .............. .............. ............. ............. ........ 117 6.2.2 bypass register (byp) .. ................ ................ ................. ................ ................. ................ .............. ........... 117 6.2.3 boundary scan r egister (bsr) ............ ................ ................. ................ ................. ............... ........... ........ 117 6.3 test access port (tap) controller ............ ................. ................ ................. .............. .............. ............. 117 7 thermal management ......... ................. ................ ................. ................. ................ ............... ........... ............ ........ 119 7.1 junction temperature ..... ................. ................ ................. ................ ................. ............... ............... ........... 119 7.2 example of junction temperature calculation ....... ................. .............. .............. .............. ............. 119 7.3 heatsink evaluation .... ................. ................ ................. ................. ................ ................. ................ ............. 119 8 physical and electrical spec ifications .......... ................. ................ ................. .............. ............. .............. 120 8.1 absolute maximum ratings ........... ................. .............. .............. .............. .............. ............... .............. ........ 120 8.2 recommended operating conditions .............. ................ ................. ................ ............... ............. ......... 121 8.3 device power consumpt ion and dissipation (typical) 1 ................. .............. .............. ............ ........ 122 8.4 device power consumpt ion and dissipation (maximum) 1 ................... ................. ................ ........... 123 8.5 d.c. characteristics .... ................. ................ ................. ................. ................ ................ ................. ............. 124 8.6 e1 receiver electrical ch aracteristics ......... ................. ................ .............. ............... .............. ........ 125 8.7 e1 transmitter electrical characteris tics ............ .............. .............. .............. .............. .............. .... 126 8.8 transmitter and receiver timing characteristics ...... .............. .............. .............. .............. ........... 12 7 8.9 clke1 timing characteristics ..... ................. ................ ............... .............. .............. .............. ............ ........ 129 8.10 jitter attenuation characteristics ................ ................ ............... .............. .............. ............. .............. 129 8.11 microprocessor interface timing .. ................. ................ ............... .............. .............. ............. .............. 132 8.11.1 serial microprocessor interface .. ................. .............. .............. .............. .............. .............. ............ ........... 132 8.11.2 parallel motorola non-mu ltiplexed microprocessor inte rface ............ .............. .............. ............ .......... ..... 134 8.11.2.1 read cycle specification ...... ................ ................. .............. .............. .............. ............. ............ 134 8.11.2.2 write cycle specification ... ................. ................ ............... .............. .............. .............. ............. 135 8.11.3 parallel intel non-multiplexed micr oprocessor interface ..... ................. ................ ............... ............ .......... 136 8.11.3.1 read cycle specification ...... ................ ................. .............. .............. .............. ............. ............ 136 8.11.3.2 write cycle specification ... ................. ................ ............... .............. .............. .............. ............. 137 8.11.4 parallel motorola multip lexed microprocessor interface ................. ................. ................ ................ ......... 138 8.11.4.1 read cycle specification ...... ................ ................. .............. .............. .............. ............. ............ 138 8.11.4.2 write cycle specification ... ................. ................ ............... .............. .............. .............. ............. 139
idt82p2521 21(+1) channel high-density e1 line interface unit table of contents 6 december 7, 2005 8.11.5 parallel intel multiplex ed microprocessor interface .... ................ ................ ................. ................ ............. 140 8.11.5.1 read cycle specification ...... ................ ................. .............. .............. .............. ............. ............ 140 8.11.5.2 write cycle specification ... ................. ................ ............... .............. .............. .............. ............. 141 8.12 jtag timing characteristics ..... ................ ................. .............. .............. .............. ............... .............. ........ 142 glossary ........... ................. ................ ................. ................ .............. ............... ............ ............. ............... .............. ......... 143 index ............... ................. ................ ................. .............. .............. .............. .............. ................... ............... .............. ......... 145 ordering information ....... ................. ................ ................. ................ ................. ................ ............... .............. ......... 147
list of tables 7 december 7, 2005 table-1 impedance matching value in receive differential mode ................................................................ ........................................................... 30 table-2 multiplex pin used in receive system interface ....................................................................... .................................................................. 33 table-3 multiplex pin used in transmit system interface ...................................................................... .................................................................. 35 table-4 puls[3:0] setting .................................................................................................... .................................................................................... 36 table-5 transmit waveform value for e1 75 ohm ................................................................................ .................................................................... 37 table-6 transmit waveform value for e1 120 ohm ............................................................................... ................................................................... 37 table-7 impedance matching value in transmit differential mode ............................................................... ........................................................... 38 table-8 exz definition ....................................................................................................... ....................................................................................... 42 table-9 llos criteria ........................................................................................................ ....................................................................................... 43 table-10 slos criteria ....................................................................................................... ........................................................................................ 44 table-11 tlos detection between two channels ................................................................................. ................................................................... 45 table-12 ais criteria ........................................................................................................ ........................................................................................... 46 table-13 rmfn indication ..................................................................................................... ...................................................................................... 51 table-14 tmfn indication ..................................................................................................... ...................................................................................... 52 table-15 clock output on clke1 ............................................................................................... ................................................................................ 60 table-16 interrupt summary ................................................................................................... .................................................................................... 66 table-17 after reset effect summary .......................................................................................... .............................................................................. 68 table-18 microprocessor interface ............................................................................................ ................................................................................. 69 list of tables
list of figures 8 december 7, 2005 figure-1 functional block diagram ............................................................................................ ................................................................................ 12 figure-2 640-pin tepbga (top view) - outline ................................................................................. ....................................................................... 13 figure-3 640-pin tepbga (t op view) - top left ................................................................................ ...................................................................... 14 figure-4 640-pin tepbga (t op view) - top right ............................................................................... ..................................................................... 15 figure-5 640-pin tepbga (top view) - bottom left ............................................................................. .................................................................... 16 figure-6 640-pin tepbga (top view) - bottom right ............................................................................ ................................................................... 17 figure-7 switch between impedance matching modes ............................................................................. ................................................................. 29 figure-8 receive differential line interface wi th twisted pair cable (with transformer) ...................................... ..................................................... 30 figure-9 receive differential line interface with coaxial cable (with transformer) ........................................... ........................................................ 30 figure-10 receive differential line in terface with twisted pair cable (tr ansformer-less, non standard compliant) ............. ...................................... 30 figure-11 receive single ended line interfac e with coaxial cable (with transformer) .......................................... .................................................... 31 figure-12 receive single ended line interface with c oaxial cable (transformer-l ess, non standard compliant) .................. ..................................... 31 figure-13 receive path monitoring ............................................................................................ ................................................................................. 32 figure-14 transmit path monitoring ........................................................................................... ................................................................................. 32 figure-15 e1 waveform template ............................................................................................... ................................................................................ 35 figure-16 e1 waveform template measurement circuit ........................................................................... ................................................................. 35 figure-17 transmit differential line interface with twisted pair cable (with transformer) .................................... .................................................... 39 figure-18 transmit differential line interfac e with coaxial cable (with transformer) ......................................... ........................................................ 39 figure-19 transmit differential line interface with twis ted pair cable (transformer-less, non standard compliant) ............ ...................................... 39 figure-20 transmit single ended line interface with coaxial cable (with transformer) ......................................... .................................................... 39 figure-21 jitter attenuator .................................................................................................. ......................................................................................... 41 figure-22 llos indication on pins ............................................................................................ .................................................................................. 43 figure-23 tlos detection between two channels ................................................................................ .................................................................... 45 figure-24 pattern generation (1) ............................................................................................. .................................................................................... 47 figure-25 pattern generation (2) ............................................................................................. .................................................................................... 47 figure-26 prbs / arb detection ............................................................................................... ................................................................................. 48 figure-27 ib detection ....................................................................................................... .......................................................................................... 49 figure-28 automatic error counter updating ................................................................................... ........................................................................... 50 figure-29 manual error counter updating ...................................................................................... ............................................................................ 50 figure-30 priority of diagnostic facilities during analog loopback ........................................................... ................................................................ 53 figure-31 priority of diagnostic fac ilities during manual remote loopback .................................................... ......................................................... 54 figure-32 priority of diagnostic facilities during digital loopback .......................................................... .................................................................. 55 figure-33 priority of diagnostic facilities during manual remote loopback + manual digital loopback .......................... ....................................... 57 figure-34 priority of diagnostic facilities duri ng manual remote loopback + automatic digital loopback ....................... ...................................... 57 figure-35 g.772 monitoring ................................................................................................... ...................................................................................... 58 figure-36 automatic jm updating .............................................................................................. ................................................................................. 59 figure-37 manual jm updating ................................................................................................. .................................................................................. 59 figure-38 refa output options in normal operation ............................................................................ .................................................................... 62 figure-39 refb output options in normal operation ............................................................................ .................................................................... 63 figure-40 refa output in llos condition (when rclkn is selected) ............................................................. ........................................................ 63 figure-41 refa output in no cl ka condition (when clka is selected) ........................................................... ...................................................... 64 figure-42 interrupt service process .......................................................................................... .................................................................................. 67 figure-43 reset .............................................................................................................. ............................................................................................. 68 figure-44 1+1 hps scheme, differential interface (shared common transformer) ................................................. ................................................. 70 figure-45 1:1 hps scheme, differentia l interface (individual transformer) .................................................... ........................................................... 71 figure-46 1+1 hps scheme, e1 75 ohm singl e-ended interface (shared common transformer) ....................................... .................................... 72 figure-47 jtag architecture .................................................................................................. ................................................................................... 117 figure-48 jtag state diagram ................................................................................................. ................................................................................ 118 list of figures
idt82p2521 21(+1) channel high-density e1 line interface unit list of figures 9 december 7, 2005 figure-49 transmit cloc k timing diagram ...................................................................................... .......................................................................... 128 figure-50 receive clock timing diagram ....................................................................................... .......................................................................... 128 figure-51 clke1 clock timing diagram ......................................................................................... .......................................................................... 129 figure-52 e1 jitter tolerance performance .................................................................................... ........................................................................... 130 figure-53 e1 jitter transfer performance ..................................................................................... ............................................................................ 131 figure-54 read operation in seri al microprocessor interface .................................................................. ................................................................ 132 figure-55 write operation in seri al microprocessor interface ................................................................. .................................................................. 132 figure-56 timing diagram ..................................................................................................... .................................................................................... 133 figure-57 parallel motorola non-multiplex ed microprocessor interface read cycle .............................................. .................................................. 134 figure-58 parallel motorola non-multiplex ed microprocessor interface write cycle ............................................. ................................................... 135 figure-59 parallel intel non-multiplexed microprocessor interface read cycle ................................................. ...................................................... 136 figure-60 parallel intel non-multiplexed microprocessor interface write cycle ................................................ ........................................................ 137 figure-61 parallel motorola multiplexed microprocessor interface read cycle .................................................. ...................................................... 138 figure-62 parallel motorola multiplexed microprocessor interface write cycle ................................................. ....................................................... 139 figure-63 parallel intel multiplexed mi croprocessor interface read cycle ..................................................... .......................................................... 140 figure-64 parallel intel multiplexed mi croprocessor interface write cycle .................................................... ........................................................... 141 figure-65 jtag timing ........................................................................................................ ..................................................................................... 142
10 december 7, 2005 idt82p2521 ? 2005 integrated device technology, inc. dsc-6976/1 21(+1) channel high-density e1 line interface unit idt and the idt logo are trademarks of integrated device technology, inc. features ! integrates 21+1 channels e1 shor t haul line interface units for 120 ? e1 twisted pair cable and 75 ? e1 coaxial cable applications ! per-channel configurable line interface options ? supports various line interface options ? differential and single ended line interfaces ? true single ended termination on primary and secondary side of trans- former for e1 75 ? coaxial cable applications ? transformer-less for differential interfaces ? fully integrated and software selectable receive and transmit termination ? option 1: fully internal impedance matching with integrated receive termination resistor ? option 2: partially internal impedance matching with common external resistor for improved device power dissipation ? option 3: external impedance matching termination ? supports global configuration and per-channel configuration to e1 mode ! per-channel programmable features ? provides e1 short haul waveform templates and user- programmable arbitrary waveform templates ? provides two jas (jitter attenuator ) for each channel of receiver and transmitter ? supports ami/hdb3 encoding and decoding ! per-channel system interface options ? supports single rail, dual rail with clock or without clock and sliced system interface ? integrated clock recovery for the transmit interface to recover transmit clock from system transmit data ! per-channel system and diagnostic functions ? provides transmit driver over -current detection and protection with optional automatic high impedance of transmit interface ? detects and generates prbs (pseudo random bit sequence), arb (arbitrary pattern) and ib (inband loopback) in either receive or transmit direction ? provides defect and alarm detection in both receive and transmit directions. ? defects include bpv (bipolar violat ion) /cv (code violation) and exz (excessive zeroes) ? alarms include llos (line los), slos (system los), tlos (transmit los) and ais (alarm indication signal) ? programmable llos detection /clear levels. compliant with itu and ansi specifications ? various pattern, defect and alarm reporting options ? serial hardware llos reporting (llos, llos0) for all 22 channels ? configurable per-channel hardware reporting with rmf/tmf (receive /transmit multiplex function) ? register access to individual registers or 16-bit error counters ? supports analog loopback, digital loopback and remote loopback ? supports t1.102 line monitor ! channel 0 monitoring options ? channel 0 can be configured as monitoring channel or regular channel to increase capacity ? supports all internal g.772 m onitoring for non-intrusive monitoring of any of the 21 channels of receiver or transmitter ? jitter measurement per itu o.171 ! hitless protection switching (h ps) without external relays ? supports 1+1 and 1:1 hitless protection switching ? asynchronous hardware control (o e, rim) for fast global high impedance of receiver and transmi tter (hot switching between working and backup board) ? high impedance transmitter and receiver while powered down ? per-channel register control for high impedance, independent for receiver and transmitter ! clock inputs and outputs ? flexible master clock (n x 2.048 mhz) (1 n 8, n is an integer number) ? two selectable reference clock outputs ? from the recovered clock of any of the 22 channels ? from external clock input ? from device master clock ? integrated clock synthesizer can mu ltiply or divide the reference clock to a wide range of frequencies: 8 khz, 64 khz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 19.44 mhz and 32.768 mhz ? cascading is provided to select a single reference clock from multiple devices without the need for any external logic ! microprocessor interface ? supports serial microprocessor interface and parallel intel / motorola non-multiplexed /multi plexed microprocessor interface ! other key features ? ieee1149.1 jtag boundary scan ? two general purpose i/o pins ? 3.3 v i/o with 5 v tolerant inputs ? 3.3 v and 1.8 v power supply ? package: 640-pin tepbga (31 mm x 31 mm) ! applicable standards ? at&t pub 62411 accunet t1.5 service ? ansi t1.102 and t1.403 ? bellcore tr-tsy-000009, gr-253-core and gr-499-core ? etsi ctr12/13 ? ets 300166 and ets 300 233 ? g.703, g.735, g.736, g.742, g.772, g.775, g.783 and g.823 ? o.161 ? itu i.431 and itu o.171
idt82p2521 21(+1) channel high-density e1 line interface unit applications 11 december 7, 2005 applications ! sdh/sonet multiplexers ! central office or pbx (private branch exchange) ! digital access cross connects ! remote wireless modules ! microwave transmission systems description the idt82p2521 is a 21+1 channels high-density e1 short haul line interface unit. each channel of the idt82p2521 can be independently configured. the configuration is per formed through a serial or parallel intel/motorola non-multiplexed /m ultiplexed microprocessor interface. in the receive path, through a single ended or differential line inter- face, the received signal is processed by an adaptive equalizer and then sent to a slicer. clock and data are recovered from the digital pulses output from the slicer. after passing through an enabled or disabled receive jitter attenuator, the recovered data is decoded using ami/ hdb3 line code rule in single rail nrz format mode and output to the system, or output to the system without decoding in dual rail nrz format mode and dual rail rz format mode. in the transmit path, the data to be transmitted is input on tdn in single rail nrz format mode or tdpn /tdnn in dual rail nrz format mode and dual rail rz format m ode, and is sampled by a transmit reference clock. the clock can be supplied externally from tclkn or recovered from the input transmit data by an internal clock recovery. a selectable ja in tx path is used to de-jitter gapped clocks. to meet e1 waveform standards, two e1 templates, as well as an arbitrary waveform generator are provided. the data through the waveform shaper, the line driver and the tx transmitte r is output on ttipn and tringn. alarms (including los, ais) and defects (including bpv, exz) are detected in both receive line side and transmit system side. ais alarm, prbs, arb and ib patterns can be generated /detected in receive / transmit direction for testing purpose. analog loopback, digital loop- back and remote loopback are all integrated for diagnostics. channel 0 is a special channel. be sides normal operation as the other 21 channels, channel 0 also supports g.772 monitoring and jitter measurement per itu o.171. a line monitor function per t1.102 is available to provide a non-intru- sive monitoring of channels of other devices. jtag per ieee 1149.1 is also supported by the idt82p2521.
idt82p2521 21(+1) channel high-density e1 line interface unit block diagram 12 december 7, 2005 block diagram figure-1 functional block diagram rx terminator amplifier slicer rx clock & data recovery rja decoder defect/alarm detector rtip[21:0] rring[21:0] llos rclk[21:0]/rmf[21:0] rdn[21:0]/rmf[21:0] rd[21:0]/rdp[21:0] llos0 tx clock recovery encoder tja waveform shaper tx terminator line driver ttip[21:0] tring[21:0] tclk[21:0]/tdn[21:0] tdn[21:0]/tmf[21:0] td[21:0]/tdp[21:0] analog loopback alarm generator digital loopback remote loopback defect/alarm detector g.772 monitor vddio vdda gnda vddd gndd gndt vddt vddr jtag trst tms tck tdi tdo clock generator mclk mcksel[3:0] clke1 refa refb clka clkb p/ s cs int/ mot int im sdo/ ack /ready sclk/ ds / rd sdi/r/ w / wr d[7:0] a[10:0] ale/as mcu interface common control oe ref rst gpio[1:0] rim vcom[1:0] vcomen pattern generator/ detector rclk[21:0]
idt82p2521 21(+1) channel high-density e1 line interface unit pin assignment 13 december 7, 2005 1 pin assignment figure-2 shows the outline of the pin assignment. for a clearer description, four segments are divi ded in this figure and the details of each are shown from figure-3 to figure-6. figure-2 640-pin tepbga (top view) - outline 110 9 8 7 6 5 4 3 212 26 25 24 23 22 21 20 19 18 17 16 15 14 13 11 29 28 27 30 110 9 8 7 6 5 4 3 212 26 25 24 23 22 21 20 19 18 17 16 15 14 13 11 29 28 27 30 a ak ah aj ag af ae ad ac ab aa y v u t r p n m l k j h g f e d c b w a ak ah aj ag af ae ad ac ab aa y v u t r p n m l k j h g f e d c b w top left top right bottom left bottom right
idt82p2521 21(+1) channel high-density e1 line interface unit pin assignment 14 december 7, 2005 figure-3 640-pin tepbga (top view) - top left gnda ttip17 ttip16 tring 19 ttip19 ttip18 vdda tring 16 nc tclk20/ tdn20 nc tclk21/ tdn21 td19/ tdp19 td17/ tdp17 rdn17/ rmf17 tclk18/ tdn18 rdn19/ rmf19 111 10 9 8 7 6 5 4 3 2 14 13 12 15 tring 20 nc nc ttip20 ttip21 ttip1 ttip0 tring0 ttip2 nc nc tring 17 gndt tring 18 vdda gndt rtip17 rring 17 rtip18 gndt rtip16 vddt 17 gndt vddt 18 vddt 19 vddt 16 vddr 17 vddr 16 rring 18 gndt rring 16 rtip19 rring 20 vddr 20 nc rring 19 vddr 19 vddr 18 vddt 20 gnda nc rtip20 vddr 21 vddt 21 nc gndt vddt0 nc gndt gndt tring 21 vdda rring 21 vddt1 vddr0 vddr1 rring0 nc vdda rtip21 tring1 nc rring1 rtip0 vddt2 vcom0 rtip1 vddt3 tring2 111 10 9 8 7 6 5 4 3 2 14 13 12 15 a r p n m l k j h g f e d c b a r p n m l k j h g f e d c b nc tdn20/ tmf20 rclk21/ rmf21 tdn21/ tmf21 rclk20/ rmf20 tdn18/ tmf18 rd19/ rdp19 nc nc vddio vddd vddd nc nc gndd gnda gnda gndd gndd gndd gndd gndd gndd gndd gndd gndd gnda gndt gndt gndt gnda gnda gnda gnda gnda gnda gnda gnda gnda rclk18/ rmf18 rd17/ rdp17 tclk17/ tdn17 rdn18/ rmf18 td18/ tdp18 tclk19/ tdn19 rdn20/ rmf20 td20/ tdp20 nc rdn21/ rmf21 td21/ tdp21 rd21/ rdp21 nc nc rd20/ rdp20 tdn19/ tmf19 rclk19/ rmf19 rd18/ rdp18 tdn17/ tmf17 vddio vddio vddio vddio gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd
idt82p2521 21(+1) channel high-density e1 line interface unit pin assignment 15 december 7, 2005 figure-4 640-pin tepbga (top view) - top right gnda ttip15 tring 15 rclk11/ rmf11 gnda rclk16/ rmf16 tdn16/ tmf16 rd15/ rdp15 30 20 21 22 23 24 25 26 27 28 29 17 18 19 16 tring 14 tring 13 nc ttip14 ttip13 nc ttip12 tring 12 tring 10 ttip11 tring 11 tclk11/ tdn11 nc rdn11/ rmf11 nc td11/ tdp11 nc gndt ref rdn12/ rmf12 tdn11/ tmf11 nc nc vddr15 vddr14 rring 15 vddt15 vddio vddr13 rtip14 nc nc nc rring 14 rtip15 vddt14 gnda nc nc gndt gndt vdda rring 13 vddt12 nc vdda gndt vddt13 vdda rtip13 nc nc vddr12 gndt gndt nc vdda nc nc rring 11 vcom1 vddt11 vddr11 rtip11 rring 10 vddt10 30 20 21 22 23 24 25 26 27 28 29 17 18 19 16 a r p n m l k j h g f e d c b a r p n m l k j h g f e d c b td13/ tdp13 nc rdn13/ rmf13 tclk12/ tdn12 rdn14/ rmf14 rdn16/ rmf16 td16/ tdp16 tclk15/ tdn15 td14/ tdp14 tclk16/ tdn16 nc td15/ tdp15 vddio nc vddd gndd gndd gndd rring 12 rtip12 gndt gnda gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd rclk14/ rmf14 tdn14/ tmf14 nc rclk13/ rmf13 tdn13/ tmf13 rd12/ rdp12 nc nc rd11/ rdp11 gnda gnda rclk17/ rmf17 rd16/ rdp16 rclk15/ rmf15 tdn15/ tmf15 rd14/ rdp14 nc nc rd13/ rdp13 rclk12/ rmf12 tdn12/ tmf12 nc td12/ tdp12 tclk13/ tdn13 nc nc tclk14/ tdn14 rdn15/ rmf15 vddd gndd vddd gndd vddd gndd vddio gndd vddio gndd vddio gndd gnda gnda gnda gnda gnda gnda gnda gnda
idt82p2521 21(+1) channel high-density e1 line interface unit pin assignment 16 december 7, 2005 figure-5 640-pin tepbga (top view) - bottom left gnda rclk3/ rmf3 rdn2/ rmf2 vdda d7 a6 a2 a10 d3 111 10 9 8 7 6 5 4 3 2 14 13 12 15 td2/ tdp2 td1/ tdp1 rdn1/ rmf1 gnda tring4 ttip4 ttip5 tring3 ttip3 nc nc vdda nc td3/ tdp3 nc rclk2/ rmf2 trst tdi tclk2/ tdn2 tdn2/ tmf2 tck vdda rclk1/ rmf1 tms gnda rd1/ rdp1 vddr5 tclk1/ tdn1 tdn1/ tmf1 rtip4 rring5 tring5 vddr4 rtip5 nc gndt rring4 vdda vddt5 rtip2 rring3 nc nc vdda rtip3 vddt4 rring2 vddr3 nc gndt vdda vddr2 nc gndt 111 10 9 8 7 6 5 4 3 2 14 13 12 15 ak t u v w y aa ab ac ad ae af ag ah aj ak t u v w y aa ab ac ad ae af ag ah aj oe td5/ tdp5 d6 a5 a1 a9 d2 rd0/ rdp0 rim rclk5/ rmf5 tdn5/ tmf5 d5 a4 a0 a8 d1 rst d4 a3 ale/as a7 d0 gpio0 gpio1 nc tdo ic int/ mot im ic ic vddio vddio gndd gndd vddd vddd vddio gndd gndd gnda gndt nc nc gnda gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gnda gnda gnda gnda gnda gnda gnda gnda nc nc nc nc nc nc rd2/ rdp2 rdn3/ rmf3 rd3/ rdp3 tclk3/ tdn3 tdn3/ tmf3 td4/ tdp4 nc nc nc rdn4/ rmf4 rd4/ rdp4 tclk4/ tdn4 tdn4/ tmf4 tclk5/ tdn5 td0/ tdp0 rdn0/ rmf0 rdn5/ rmf5 tclk0/ tdn0 rclk0/ rmf0 tdn0/ tmf0 rd5/ rdp5 rclk4/ rmf4
idt82p2521 21(+1) channel high-density e1 line interface unit pin assignment 17 december 7, 2005 figure-6 640-pin tepbga (top view) - bottom right gnda nc rdn10/ rmf10 gnda sclk/ ds / rd int refa mclk 30 20 21 22 23 24 25 26 27 28 29 17 18 19 16 ttip6 tring7 ttip7 tring6 nc ttip9 tring8 ttip8 ttip10 nc tring9 gnda nc nc tclk10/ tdn10 rclk10/ rmf10 tclk9/ tdn9 nc tdn10/ tmf10 rd10/ rdp10 tdn9/ tmf9 vddr7 vcome n vddr6 vddt6 nc vddr8 rring7 rring6 gndt nc rtip7 rtip6 gndt gnda nc gnda nc vddt7 vdda rtip8 vddt8 nc gnda gndt nc vdda rring8 vddt9 nc nc gndt gndt rring9 gnda gndt vddr9 nc gndt nc vddr10 nc rtip10 nc 30 20 21 22 23 24 25 26 27 28 29 17 18 19 16 ak t u v w y aa ab ac ad ae af ag ah aj ak t u v w y aa ab ac ad ae af ag ah aj cs sdo/ ack / rdy refb clka sdi/r/ w / wr ic clkb p/ s clke1 mcksel 3 mcksel 2 gndd gndd mcksel 1 llos nc llos0 mcksel 0 vddio vddd vddio vddio vddd vddio vddio vddio vddd gnda vdda vdda rtip9 gnda gnda gnda gnda gnda gnda gnda gnda gnda gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd gndd rclk9/ rmf9 td10/ tdp10 nc nc nc rdn9/ rmf9 rd9/ rdp9 td9/ tdp9 rclk8/ rmf8 rdn8/ rmf8 td8/ tdp8 nc rdn7/ rmf7 td7/ tdp7 tclk6/ tdn6 tdn6/ tmf6 rclk6/ rmf6 rd7/ rdp7 nc nc rd8/ rdp8 tclk8/ tdn8 nc nc tclk7/ tdn7 rdn6/ rmf6 td6/ tdp6 rd6/ rdp6 tdn7/ tmf7 rclk7/ rmf7 nc tdn8/ tmf8
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 18 december 7, 2005 2 pin description name i / o pin no. 1 description line interface rtipn rringn (n=0~21) input p3, r5, v4, w5, aa4, ab5, ae28, ae26, aa26, w28, t28, r26, l28, l26, g26, f28, d6, d4, d3, g4, h5, m5 n3, p5, u4, v5, y4, aa5, ad28, ad26, y26, w27, r28, p26, k28, k26, f26, e28, e6, d5, e3, f4, g5, l5 rtipn / rringn: receive bipolar tip/ring for channel 0 ~ 21 the receive line interface supports both receive differential mode and receive single ended mode. in receive differential mode, the received signal is coupled into rtipn and rringn via a 1:1 transformer or without a transformer (transformer-less). in receive single ended mode, rringn should be left open. the received signal is input on rtipn via a 2:1 (step down) transformer or without a transformer (transformer-less). these pins will become high-z globally or channel specific in the following conditions: ? global high-z: - connecting the rim pin to low; - loss of mclk - during and after power-on reset, hardware reset or global software reset; ? per-channel high-z - receiver power down by writing ?1? to the r_off bit (b5, rcf0,...) ttipn tringn (n=0~21) output l1, m1, r1, u1, y1, aa1, af30, ad30, aa30, w30, t30, p30, l30, j30, f30, d30, a5, a4, a3, c1, f1, j1 k1, m2, r2, t1, w1, aa2, ae30, ac30, y30, v30, r30, n30, k30, h30, e30, c30, a6, b4, b3, d1, e1, j2 ttipn / tringn: transmit bipolar tip /ring for channel 0 ~ 21 the transmit line interface supports both transmit differential mode and transmit single ended mode. in transmit differential mode, ttipn outputs a positive differential pulse while tringn out- puts a negative differential pulse. the pulses are coupled to the line side via a 1:2 (step up) transformer or without a transformer (transformer-less). in transmit single ended mode, tringn should be left open (it is shorted to ground inter- nally). the signal presented at ttipn is output to the line side via a 1:2 (step up) transformer. these pins will become high-z globally or channel specific in the following conditions: ? global high-z: - connecting the oe pin to low; - loss of mclk; - during and after power-on reset, hardware reset or global software reset; ? per-channel high-z - writing ?0? to the oe bit (b6, tcf0,...) 2 ; - loss of tclkn in transmit single rail nrz format mode or transmit dual rail nrz format mode, except that the channel is in remote loopback or transmit internal pat- tern with xclk 3 ; - transmitter power down by writing ?1? to the t_off bit (b5, tcf0,...); - per-channel software reset; - the thz_oc bit (b4, tcf0,...) is set to ?1? and the transmit dr iver over-current is detected. refer to section 3.2.8 output high-z on ttip and tring for details. note: 1. the pin number of the pins with the footnote ?n ? is listed in order of channel (ch0 ~ ch21). 2. the content in the brackets indicates the position and the register name of the preceding bit. af ter the register name, if the punctuation ?,...? is followed, this bit is in a per-channel register. if there is no punctuation following the address, this bit is in a global register or in a c hannel 0 only register. the address es and details are included in chapter 5 programming information. 3. xclk is derived from mclk. it is 2.048 mhz.
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 19 december 7, 2005 name i / o pin no. description system interface rdn / rdpn (n=0~21) output ah9, ac4, ag1, ah3, ah6, ak8, ak20, ah21, ah24, ak26, ah29, a27, a24, c23, c20, a18, c17, b15, d14, b12, d11, d8 rdn: receive data for channel 0 ~ 21 when the receive system interface is configured to single rail nrz format mode, this multi- plex pin is used as rdn. the decoded nrz data is updated on the active edge of rclkn. the active level on rdn is selected by the rd_inv bit (b3, rcf1,...). when the receiver is powered down, rdn will be in high-z state or low, as selected by the rhz bit (b6, rcf0,...). rdpn: positive receive data for channel 0 ~ 21 when the receive system interface is configured to dual rail nrz format mode, dual rail rz format mode or dual rail sliced mode, this multiplex pin is used as rdpn. in receive dual rail nrz format mode, the un-decoded nrz data is output on rdpn and rdnn and updated on the active edge of rclkn. in receive dual rail rz format mode, the un-decoded rz data is output on rdpn and rdnn and updated on the active edge of rclkn. in receive dual rail sliced mode, the raw rz sliced data is output on rdpn and rdnn. for receive differential line interface, an active level on rdpn indicates the receipt of a posi- tive pulse on rtipn and a negative pulse on rringn; while an active level on rdnn indi- cates the receipt of a negative pulse on rtipn and a positive pulse on rringn. for receive single ended line interface, an active level on rdpn indicates the receipt of a positive pulse on rtipn; while an active level on rdnn indicates the receipt of a negative pulse on rtipn. the active level on rdpn and rdnn is selected by the rd_inv bit (b3, rcf1,...). when the receiver is powered down, rdpn and rdnn will be in high-z state or low, as selected by the rhz bit (b6, rcf0,...). rdnn / rmfn (n=0~21) output ag9, ad1, ah1, ag3, ag6, aj8, aj20, ag21, ag24, aj26, ah30, b28, d25, b23, b20, d19, b17, a15, c14, a12, c11, c8 rdnn: negative receive data for channel 0 ~ 21 when the receive system interface is configured to dual rail nrz format mode, dual rail rz format mode or dual rail sliced mode, this multiplex pin is used as rdnn. (refer to the description of rdpn for details). rmfn: receive multiplex function for channel 0 ~ 21 when the receive system interface is configured to single rail nrz format mode, this multi- plex pin is used as rmfn. rmfn is configured by the rmf_def[2:0] bits (b7~5, rcf1,...) and can indicate prbs/arb, lais, lexz, lbpv, lexz+lbpv, llos, output recovered clock (rclk) or xor output of positive and negative sliced data. refer to se ction 3.4.7.1 rmfn indication for details. the output on rmfn is updated on the active edge of rclkn. the active level of rmfn is always high. when the receiver is powered down, rmfn will be in high-z state or low, as selected by the rhz bit (b6, rcf0,...).
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 20 december 7, 2005 rclkn / rmfn (n=0~21) output ak10, ad2, ah 2, ak4, ak7, ah8, ah20, ak22, ak25, ah26, ag29, a28, c25, a23, a20, c19, a17, c16, b14, d13, b11, b8 rclkn: receive clock for channel 0 ~ 21 when the receive system interface is configured to single rail nrz format mode, dual rail nrz format mode or dual rail rz format mode, this multiplex pin is used as rclkn. rclkn outputs a 2.048 mhz clock which is recovered from the received signal. the data output on rdn and rmfn (in receive single rail nrz format mode) or rdpn/ rdnn (in receive dual rail nrz format mode, receive dual rail rz format mode and receive dual rail sliced) is updated on the active edge of rclkn. the active edge is selected by the rck_es bit (b4, rcf1,...). in llos condition, rclkn output high or xclk, as selected by the rckh bit (b7, rcf0 ,...) (refer to section 3.4.3.1 line los (llos) for details). when the receiver is powered down, rclkn will be in high-z state or low, as selected by the rhz bit (b6, rcf0,...). rmfn: receive multiplex function for channel 0 ~ 21 when the receive system interface is configured to dual rail sliced mode, this multiplex pin is used as rmfn. (refer to the description of rmfn of the rdnn/rmfn multiplex pin for details). llos output af17 llos: receive line loss of signal llos synchronizes with the output of clke1 and can indicate the llos (line los) status of all 22 channels in a serial format. when the clock output on clke1 is enabled, llos indicates the llos status of the 22 chan- nels in a serial format and repeats every twenty-two cycles. channel 0 is positioned by llos0. refer to the description of llos0 below for details. the last 7 redundant clock cycles are low and should be ignored. llos is updated on the rising edge of clke1 and is always active high. when the clock output of clke1 is disabled, llos will be held in high-z state. (refer to section 3.4.3.1 line los (llos) for details.) llos0 output af18 llos0: receive line loss of signal for channel 0 llos0 can indicate the position of channel 0 on the llos pin. when the clock output on clke1 is enabled, llos0 pulses high for one clke1 clock cycle to indicate the position of channel 0 on the llos pin. when clke1 outputs 8 khz clock, llos0 pulses high for one 8 khz clock cycle (125 s) every twenty-nine 8 khz clock cycles; when clke1 outputs 2.048 mhz clock, llos0 pulses high for one 2.048 mhz clock cycle (488 ns) every twenty-nine 2.048 mhz clock cycles. llos0 is updated on the rising edge of clke1. when the clock output on clke1 is disabled, llos0 will be held in high-z state. (refer to section 3.4.3.1 line los (llos) for details.) name i / o pin no. description
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 21 december 7, 2005 tdn / tdpn (n=0~21) input ag8, ac1, af1, ag2, ag5, aj7, aj19, ag20, ag23, aj25, aj28, d27, d24, b22, b19, d18, b16, a14, c13, a11, c10, c7 tdn: transmit data for channel 0 ~ 21 when the transmit system interface is configured to single rail nrz format mode, this multi- plex pin is used as tdn. tdn accepts single rail nrz data. the data is sampled into the device on the active edge of tclkn. the active level on tdn is selected by the td_inv bit (b3, tcf1,...). tdpn: positive transmit data for channel 0 ~ 21 when the transmit system interface is configured to dual rail nrz format mode or dual rail rz format mode, this multiplex pin is used as tdpn. in transmit dual rail nrz format mode, the pre-encoded nrz data is input on tdpn and tdnn and sampled on the active edge of tclkn. in transmit dual rail rz format mode, the pre-encoded rz data is input on tdpn and tdnn. the line code is as follows (when the td_inv bit (b3, tcf1,...) is ?0?): the active level on tdpn and tdnn is selected by the td_inv bit (b3, tcf1,...). tdnn / tmfn (n=0~21) input / output ak9, ac2, af2, ak3, ak6, ah7, ah19, ak21, ak24, ah25, ah28, c27, c24, a22, a19, c18, a16, d15, b13, d12, b10, b7 tdnn: negative transmit data for channel 0 ~ 21 when the transmit system interface is configured to dual rail nrz format mode, this multi- plex pin is used as tdnn. (refer to the description of tdpn for details). tmfn: transmit multiplex function for channel 0 ~ 21 when the transmit system interface is configured to single rail nrz format mode or dual rail rz format mode, this multiplex pin is used as tmfn. tmfn is configured by the tmf_def[2:0] bits (b7~5, tcf1,...) and can indicate prbs/arb, sais, toc, tlos, sexz, sbpv, sexz+sbpv, slos. refer to section 3.4.7.2 tmfn indica- tion for details. the output on tmfn is updated on the active edge of tclkn (if available). the active level of tmfn is always high. tclkn / tdnn (n=0~21) input aj9, ac3, af3, aj3, aj6, ag7, ag19, aj21, aj24, ag25, ag28, b27, b24, d23, d20, b18, d17, c15, a13, c12, a10, a7 tclkn: transmit clock for channel 0 ~ 21 when the transmit system interface is configured to single rail nrz format mode or dual rail nrz format mode, this multiplex pin is used as tclkn. tclkn inputs a 2.048 mhz clock. the data input on tdn (in transmit single rail nrz format mode) or tdpn/tdnn (in trans- mit dual rail nrz format mode) is sampled on the active edge of tclkn. the data output on tmfn (in transmit single rail nrz format mode) is updated on the active edge of tclkn. the active edge is selected by the tck_es bit (b4, tcf1,...). tdnn: negative transmit data for channel 0 ~ 21 when the transmit system interface is configured to dual rail rz format mode, this multiplex pin is used as tdnn. (refer to the description of tdpn for details). name i / o pin no. description tdpn tdnn output pulse on ttipn output pulse on tringn * 0 0 space space 0 1 negative pulse positive pulse 1 0 positive pulse negative pulse 1 1 space space note: * for transmit single ended line interface, tringn should be open.
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 22 december 7, 2005 clock mclk input ak19 mclk: master clock input mclk provides a stable reference timing for the idt82p2521. mclk should be a jitter-free 1 clock with 50 ppm accuracy. the clock frequency of mclk is informed to the device by mcksel[3:0]. if mclk misses (duty cycle is less than 30% for 10 s) and then recovers, the device will be reset automatically. mcksel[0] mcksel[1] mcksel[2] mcksel[3] input af19 af20 af21 af22 mcksel[3:0]: master clock selection these four pins inform the device of the clock frequency input on mclk: clke1 output ag18 clke1: 8 khz / e1 clock output the output on clke1 can be enabled or disabled, as determined by the clke1_en bit (b3, clkg). when the output is enabled, clke1 outputs an 8 khz or 2.048 mhz clock, as selected by the clke1 bit (b2, clkg). the output is locked to mclk. when the output is disabled, clke1 is in high-z state. refa output ak18 refa: reference clock output a refa can output three kinds of clocks: a recovered clock of one of the 22 channels, an exter- nal clock input on clka or a free running clock. the clock frequency is programmable. refer to section 3.5.2 clock outputs on refa/refb for details. the output on refa can also be disabled, as determined by the refa_en bit (b6, refa). when the output is disabled, refa is in high-z state. name i / o pin no. description mcksel[3:0] * frequency (mhz) 1000 2.048 1001 2.048 x 2 1010 2.048 x 3 1011 2.048 x 4 1100 2.048 x 5 1101 2.048 x 6 1110 2.048 x 7 1111 2.048 x 8 others don?t care note: 0: gndd 1: vddio note: 1. jitter is no more than 0.001 ui.
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 23 december 7, 2005 refb output aj18 refb: reference clock output b refb can output a recovered clock of one of the 22 channels, an external clock input on clkb or a free running clock. refer to section 3.5.2 clock outputs on refa/refb for details. the output on refb can also be disabled, as determined by the refb_en bit (b6, refb). when the output is disabled, refb is in high-z state. clka input ah17 clka: external e1 clock input a external e1 clock is input on this pin. the cka_e1 bit (b5, refa) should be set to match the clock frequency. when not used, this pin should be connected to gndd. clkb input ag17 clkb: external e1 clock input b external e1 clock is input on this pin. the ckb_e1 bit (b5, refb) should be set to match the clock frequency. when not used, this pin should be connected to gndd. common control vcom[0] vcom[1] output r4 p28 vcom: voltage common mode [1:0] these pins are used only when the receive line interface is in receive differential mode and connected without a transformer (transformer-less). to enable these pins, the vcomen pin must be connected high. refer to figure-10 for the connection. when these pins are not used, they should be left open. vcomen input (pull-down) af26 vcomen: voltage common mode enable this pin should be connected high only when the receive line interface is in receive differen- tial mode and connected without a transformer (transformer-less). when not used, this pin should be left open. ref - d29 ref: reference resistor an external resistor (10 k ? , 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit. this resistor is required to ensure correct device opera- tion. rim input (pull-down) ah10 rim: receive impedance matching in receive differential mode, when rim is low, all 22 receivers become high-z and only exter- nal impedance matching is supported. in this case, the per-channel impedance matching con- figuration bits - the r_term[2:0] bits (b2~0, rcf0,...) and the r120in bit (b4, rcf0,...) - are ignored. in receive differential mode, when rim is high, impedance matching is configured on a per- channel basis by the r_term[2:0] bits (b2~0, rcf0,...) and the r120in bit (b4, rcf0,...). this pin can be used to control the receive impedance state for hitless protection applica- tions. refer to section 4.4 hitless protection switching (hps) summary for details. in receive single ended mode, this pin should be left open. oe input aj10 oe: output enable oe enables or disables all line drivers globally. a high level on this pin enables all line drivers while a low level on this pin places all line drivers in high-z state and independent from related register settings. note that the functionality of the internal circuit is not affected by oe. if this pin is not used, it should be tied to vddio. this pin can be used to control the transmit impedance state for hitless protection applica- tions. refer to section 4.4 hitless protection switching (hps) summary for details. name i / o pin no. description
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 24 december 7, 2005 gpio[0] gpio[1] output / input af9 af10 gpio: general purpose i/o [1:0] these two pins can be defined as input pins or output pins by the dir[1:0] bits (b1~0, gpio) respectively. when the pins are input , their polarities are indicated by the level[1:0] bits (b3~2, gpio) respectively. when the pins are output, their polarities are controlled by the level[1:0] bits (b3~2, gpio) respectively. rst input ag10 rst : reset (active low) a low pulse on this pin resets the device. this hardware reset process completes in 2 s max- imum. refer to section 4.1 reset for an overview on reset options. mcu interface int output ak16 int : interrupt request this pin indicates interrupt requests for all unmasked interrupt sources. the output characteristics (open drain or push-pull internally) and the active level are deter- mined by the int_pin[1:0] bits (b3~2, gcf). cs input aj17 cs : chip select (active low) this pin must be asserted low to enable the microprocessor interface. a transition from high to low must occur on this pin for each read/write operation and cs should remain low until the operation is over. p/ s input ag16 p/ s : parallel or serial microprocessor interface select p/ s selects serial or parallel microprocessor interface for the device: gndd - serial microp rocessor interface. vddio - parallel micr oprocessor interface. serial microprocessor interface consists of the cs , sclk, sdi, sdo pins. parallel microprocessor interface consists of the cs , int/ mot , im, ds / rd , ale/as, r/ w / wr , ack /rdy, d[7:0], a[10:0] pins. int/ mot input (pull-up) af14 int/ mot : intel or motorola microprocessor interface select in parallel micropro cessor interface, int/ mot selects intel or motorola microprocessor inter- face for the device: gndd - parallel motorola microprocessor interface. open - parallel intel microprocessor interface. in serial microprocessor interface, this pin should be left open. im input (pull-up) af15 im: interface mode selection in parallel motorola or intel microprocessor interface, im selects multiplexed bus or non-multi- plexed bus for the device: gndd - parallel motorola /intel non-multiplexed microprocessor interface. open - parallel motorola /intel multiplexed microprocessor interface. in serial microprocessor interface, this pin should be connected to gndd. ale / as input ag15 ale: address latch enable in parallel intel multiplexed microprocessor interface, this multiplex pin is used as ale. the address on a[10:8] and d[7:0] (a[7:0] are ignored) is sampled into the device on the fall- ing edges of ale. as: address strobe in parallel motorola multiplexed microprocessor interface, this multiplex pin is used as as. the address on a[10:8] and d[7:0] (a[7:0] are ignored) is latched into the device on the falling edges of as. in parallel motorola /intel non-multiplexed microprocessor interface, this pin should be pulled high. in serial microprocessor interface, this pin should be connected to gndd. name i / o pin no. description
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 25 december 7, 2005 sclk / ds / rd input ak17 sclk: shift clock in serial microprocessor interface, this multiplex pin is used as sclk. sclk inputs the shift clock for the serial microprocessor interface. data on sdi is sampled by the device on the rising edge of sclk. data on sdo is updated on the falling edge of sclk. ds : data strobe (active low) in parallel motorola microprocessor interface, this multiplex pin is used as ds . during a write operation (r/ w = 0), data on d[7:0] is sampled into the device. during a read operation (r/ w = 1), data is driven to d[7:0] by the device. rd : read strobe (active low) in parallel intel microprocessor interface, this multiplex pin is used as rd . rd is asserted low by the microprocessor to initiate a read operation. data is driven to d[7:0] by the device during the read operation. sdi / r/ w / wr input ah16 sdi: serial data input in serial microprocessor interface, this multiplex pin is used as sdi. address and data on this pin are serially clocked into the device on the rising edge of sclk. r/ w : read / write select in parallel motorola microprocessor interface, this multiplex pin is used as r/ w . r/ w is asserted low for write operation or high for read operation. wr : write strobe (active low) in parallel intel microprocessor interface, this multiplex pin is used as wr . wr is asserted low by the microprocessor to initiate a write operation. data on d[7:0] is sam- pled into the device during a write operation. sdo / ack / rdy output aj16 sdo: serial data output in serial microprocessor interface, this multiplex pin is used as sdo. data on this pin is serially clocked out of the device on the falling edge of sclk. ack : acknowledge out put (active low) in parallel motorola microprocessor interface, this multiplex pin is used as ack . a low level on ack indicates that valid information on the data bus is ready for a read opera- tion or acknowledges the acceptance of the written data during a write operation. rdy: ready output in parallel intel microprocessor interface, this multiplex pin is used as rdy. a high level on rdy reports to the microprocessor that a read/write cycle can be completed. a low level on rdy reports that wait states must be inserted. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] output / input ag12 ah12 aj12 ak12 ag11 ah11 aj11 ak11 d[7:0]: bi-directional data bus in parallel motorola /intel non-multiplexed microprocessor interface, these pins are the bi- directional data bus of the microprocessor interface. in parallel motorola /intel multiplexed microprocessor interface, these pins are the multiplexed bi-directional address /data bus. in serial microprocessor interface, these pins should be connected to gndd. name i / o pin no. description
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 26 december 7, 2005 a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] input ah15 aj15 ak15 ag14 ah14 aj14 ak14 ag13 ah13 aj13 ak13 a[10:0]: address bus in parallel motorola /intel non-multiplexed microprocessor interface, these pins are the address bus of the microprocessor interface. in parallel motorola /intel multiplexed microprocessor interface, a[10:8], together with d[7:0], are the address bus; while a[7:0] should be connected to gndd. in serial microprocessor interface, these pins should be connected to gndd. jtag (per ieee 1149.1) trst input pull-down af4 trst : jtag test reset (active low) a low signal on this pin resets the jtag test port. to ensure deterministic operation of the test logic, tms should be held high when the signal on trst changes from low to high. this pin may be left unconnected when jtag is not used. this pin has an internal pull-down resistor. tms input pull-up ae5 tms: jtag test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. to ensure deterministic operation of the test logic, tms should be held high when the signal on trst changes from low to high. this pin may be left unconnected when jtag is not used. this pin has an internal pull-up resistor. tck input af6 tck: jtag test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is updated on the falling edge of tck. when tck is idle at low state, all stored-state devices contained in the test logic shall retain their state indefinitely. this pin should be connected to gndd when jtag is not used. tdi input pull-up af5 tdi: jtag test data input the test data is input on this pin. it is clocked into the device on the rising edge of tck. this pin has an internal pull-up resistor. this pin may be left unconnected when jtag is not used. tdo output af7 tdo: jtag test data output the test data is output on this pin. it is clocked out of the device on the falling edge of tck. tdo is a high-z output signal except during the process of data scanning. power & ground vddio e7, e8, e10, e11, e12, e21, e22, e23, e24, e25, ae9, ae10, ae15, ae16, ae17, ae18, ae22, ae23, ae24 vddio: 3.3 v i/o power supply vdda a2, b2, j26, k27, l4, l27, m4, m26, t4, w4, y5, y27, y28, aa27, aa28, ad5, aj2, ak2 vdda: 3.3 v analog core power supply vddd e14, e15, e16, e17, e18, e19, ae11, ae14, ae19, ae20, ae21 vddd: 1.8 v digital core power supply vddrn (n=0~21) n4, n5, t5, u5, ab4, ac5, af28, af27, ad27, u27, t27, r27, n26, g27, e26, e27, e5, e4, f3, f5, g3, h3 vddrn: 3.3 v power supply for receiver name i / o pin no. description
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 27 december 7, 2005 vddtn (n=0~21) k2, l2, p2, r3, w2, y2, af29, ac29, aa29, y29, r29, p29, k29, j29, f29, e29, c6, c4, c3, c2, f2, h2 vddtn: 3.3 v power supply for transmitter driver gnda a1, a29, a30, b1, b29, b30, f6, f7, f8, f25, g6, g25, h6, h25, j6, j25, k6, k25, l6, l25, m6, m25, n6, n25, p6, p25, r6, r25, t6, t25, u6, u25, v6, v25, w6, w25, w26, y6, y25, aa6, aa25, ab1, ab6, ab25, ab26, ac6, ac25, ac26, ad6, ad25, ae6, ae25, aj1, aj29, aj30, ak1, ak29, ak30 gnda: gnd for analog core / receiver gndd f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, m12, m13, m14, m15, m16, m17, m18, m19, n12, n13, n14, n15, n16, n17, n18, n19, p12, p13, p14, p15, p16, p17, p18, p19, r12, r13, r14, r15, r16, r17, r18, r19, t12, t13, t14, t15, t16, t17, t18, t19, u12, u13, u14, u15, u16, u17, u18, u19, v12, v13, v14, v15, v16, v17, v18, v19, w12, w13, w14, w15, w16, w17, w18, w19, ae7, ae8, ae12, ae13, af23, af24 gndd: digital gnd gndt b5, b6, c5, d2, d28, e2, h28, h29, j3, j5, j28, k3, k5, l3, m3, m28, n28, n29, t2, u2, u28, v28, v29, w29, aa3, ab2, ab28, ad29, ae29 gndt: analog gnd for transmitter driver test ic - af13, af12 ic: internal connected this pin is for idt use only and should be c onnected to gndd. ic - ah18, af11 ic: internal connected this pin is for idt use only and should be left open. name i / o pin no. description
idt82p2521 21(+1) channel high-density e1 line interface unit pin description 28 december 7, 2005 others nc - a8, a9, a21, a25, a26, b9, b21, b25, b26, c9, c21, c22, c26, c28, c29, d7, d9, d10, d16, d21, d22, d26, e9, e13, e20, f9, f27, g1, g2, g28, g29, g30, h1, h4, h26, h27, j4, j27, k4, l29, m27, m29, m30, n1, n2, n27, p1, p4, p27, t3, t26, t29, u3, u26, u29, u30, v1, v2, v3, v26, v27, w3, y3, ab3, ab27, ab29, ab30, ac27, ac28, ad3, ad4, ae1, ae2, ae3, ae4, ae27, af8, af16, af25, ag4, ag22, ag26, ag27, ag30, ah4, ah5, ah22, ah23, ah27, aj4, aj5, aj22, aj23, aj27, ak5, ak23, ak27, ak28 nc: not connected name i / o pin no. description
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 29 december 7, 2005 3 functional description 3.1 receive path 3.1.1 r x termination the receive line interface suppor ts receive differential mode and receive single ended mode, as selected by the r_sing bit (b3, rcf0,...). in receive differential mode, both rtipn and rringn are used to receive signal from the line side. in receive single ended mode, only rtipn is used to receive signal. in receive differential mode, t he line interface can be connected with e1 120 ? twisted pair cable or e1 75 ? coaxial cable. in receiver single ended mode, the line interf ace can only be connected with 75 ? coaxial cable. the receive impedance matching is r ealized by using internal imped- ance matching or external impedance matching for each channel in different applications. 3.1.1.1 receive differential mode in receive differential mode, three kinds of impedance matching are supported: fully internal impedance ma tching, partially internal imped- ance matching and external impedanc e matching. figure-7 shows an overview of how these impedanc e matching modes are switched. fully internal impedance matching ci rcuit uses an internal program- mable resistor (im) only and does not use an external resistor. this configuration saves external co mponents and supports 1:1 hitless protection switching (hps) applicat ions without relays. refer to section 4.4 hitless protecti on switching (hps) summary. partially internal impedance matching circuit consists of an internal programmable resistor (i m) and a value-fixed 120 ? external resistor (rr). compared with fully internal impedance matching, this configura- tion provides considerable savings in power dissipation of the device. for example, in e1 120 ? prbs mode, the power savings would be 0.57 w. for power savings in other modes, please refer to chapter 8 physical and electric al specifications. external impedance matching circuit uses an external resistor (rr) only. figure-7 switch between impedance matching modes to support some particular applicati ons, such as hot-swap or hitless protection switch (hps) hot-switchov er, rtipn/rringn must be forced to enter high impedance state (i.e., external impedance matching). for hot-swap, rtipn/rringn must be always held in high impedance state during /after power up; for hps hot-switchover, rtipn/rringn must enter high impedance state immediat ely after switchover. though each channel can be individually configur ed to external impedance matching through register access, it is too sl ow for hitless switch. therefore, a hardware pin - rim - is provided to globally control the high impedance for all 22 receivers. when rim is low, only external impedance matching is supported for all 22 receivers and the per-channel impedance matching configuration bits - the r_term[2:0] bits (b2~ 0, rcf0,...) and the r120in bit (b4, rcf0,...) - are ignored. when rim is high, impedance matching is configured on a per- channel basis. three kinds of impedance matching are all supported and selected by the r_term[2:0] bits (b2~0, rcf0,...) and the r120in bit (b4, rcf0,...). the r_term[2] bit (b2, rcf0,...) should be set to match internal or external impedance. if the r_term[2] bit (b2, rcf0,...) is ?0?, internal impedance matching is enabled. the r120in bit (b4, rcf0,...) should be set to se lect partially internal impedance matching or fully internal impedance matching. the internal program- mable resistor (im) is determined by the r_term[1:0] bits (b1~0, rcf0,...). if the r_term[2] bit (b2, rcf0,...) is ?1?, external impedance matching is enabled. the configurati on of the r120in bit (b4, rcf0,...) and the r_term[1:0] bits (b1~0, rcf0,...) is ignored. a twisted pair cable can be connec ted with a 1:1 transformer or without a transformer (transformer-l ess), while a coaxial cable must be connected with a 1:1 transformer. table 1 lists the recommended imped- ance matching value in different appl ications. figure-8 to figure-10 show the connection for one channel. im rtip rring rin r_term2 1 0 1 0 0 1 receive path r_term[1:0] rim r120in rr = 120 ?
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 30 december 7, 2005 the transformer-less connection will offer a termination option with reduced cost and board space. however, the waveform amplitude is not standard compliant, and surge protection and common mode depres- sion should be enhanced depending on equipment environment. figure-8 receive differential line interface with twist- ed pair cable (with transformer) figure-9 receive differenti al line interface with coax- ial cable (with transformer) figure-10 receive differe ntial line interface with twisted pair cable (transformer-less, non standard compliant) table-1 impedance matching value in receive differential mode cable condition partially internal impedance matching (r120in = 0) 1 fully internal impedance matching (r120in = 1) 1, 2 external impedance matching r_term[2:0] rr r_term[2:0] rr r_term[2:0] 3 rr e1 120 ? twisted pair (with transformer) 010 120 ? 010 (open) 1xx 120 ? e1 75 ? coaxial (with transformer) 011 011 75 ? e1 120 ? twisted pair (transformer-less 4 ) 010 (not supported) 120 ? note: 1. partially internal impedance matching and fully inte rnal impedance matching are no t supported when rim is low. 2. fully internal impedance matching is not supported in transformer-less applications. 3. when rim is low, the setting of the r_term[2:0] bits is ignored. 4. in transformer-less applications, the device should be protected against overvolt age. there are three im portant standards fo r overvoltage protection: ? ul1950 and fcc part 68; ? telcordia (bellcore) gr-1089 ? itu-t k.20, k.21 and k.41 1:1 rr rtipn rringn im 6.0 vpp 1:1 rr rtipn rringn im 4.74 vpp im 6.0vpp rtipn rringn rr/2 rr/2 vcom1 10 f 1. two rr/2 resistors should be connected to vcom[1:0] that are coupled to ground via a 10 f capacitor, which provide 60 ? common mode input resistance. 2. in this mode, lightning protection should be enhanced. 3. the maximum input dynamic range of rtip/tring pin is -0.3 v ~3.6 v (in line monitor mode it is -0.3 v ~ 2 v) note: vcom0
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 31 december 7, 2005 3.1.1.2 receive single ended mode receive single ended mode can only be used in 75 ? coaxial cable applications. in receive single ended mode, only external impedance matching is supported. external impedance matc hing circuit uses an external resistor (rr) only. the value of the resistor is 18.75 ? (see figure-11 for details) when the single end is connected with a 2:1 transformer or is 75 ? (see figure-12 for details) when the single end is connected without a transformer. in receive single ended mode, the rim pin should be left open and the configuration of the r_term[2:0] bits (b2~0, rcf0,...) is ignored. figure-11 receive single ended line interface with co- axial cable (wit h transformer) figure-12 receive single ended line interface with co- axial cable (trans former-less, non st andard compliant) 2:1 rr rtipn rringn 4.74 vpp 470 nf im rr2 rtipn rringn 4.74 vpp 470 nf rr1 rr = rr1 + rr2 = 75 ? in this mode, port protection should be enhanced. note: im
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 32 december 7, 2005 3.1.2 equalizer the equalizer compensates high frequency attenuation to enhance receive sensitivity. 3.1.2.1 line monitor in e1 short haul applications, the protected non-intrusive monitoring per t1.102 can be performed betw een two devices. the monitored channel of one device is in norma l operation, and the monitoring channel of the other device taps the monitored one through a high impedance bridging circuit (refer to figure-13 and figure-14). after the high resistance bridging circ uit, the signal arriving at rtipn/ rringn of the monitoring channel is dramatically attenuated. to compensate this bridge resistive a ttenuation, monitor gain can be used to boost the signal by 20 db, 26 db or 32 db, as selected by the mg[1:0] bits (b1~0, rcf2,...). for normal oper ation, the monitor gain should be set to 0 db, i.e., the monitor gain of the monitored channel should be 0 db. the monitoring channel can be confi gured to any of the external, partially internal or fully inter nal impedance matching mode. here the external r or internal im is us ed for voltage division, not for impedance matching. that is, the r (im) and the two r make up of a resistance bridge. the resistive attenuation of this bridge is 20lg(r/(2r+r)) db. note that line monitor is only ava ilable in differential line interface. a channel 0 monitoring function is provided (refer to section 3.4.9 channel 0 monitoring). if multiple high-density lius are used in an application, the g.772 function of c hannel 0 can be used to route the signals of channel 1~21 receive and transmit to channel 0 of the same device. this channel 0 transmit tt ip and ttring could then be moni- tored by another device through the line monitor function. 3.1.2.2 receive sensitivity the receive sensitivity is the mi nimum range of receive signal level for which the receiver recovers data error-free with -18 db interference signal added. for receive differential line interfac e, the receive sensitivity is -15 db. for receive single ended line interface, the receive sensitivity is -12 db. figure-13 receive path monitoring figure-14 transmit path monitoring rtipn rringn rtipn rringn monitored channel monitoring channel dsx cross connect point r monitor gain = 20/26/32 db monitor gain = 0 db r r ttipn tringn rtipn rringn monitored channel monitoring channel dsx cross connect point r monitor gain = 20/26/32 db monitor gain = 0 db r r
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 33 december 7, 2005 3.1.3 slicer the slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. the input signal is sliced at 50% of the peak value. 3.1.4 r x clock & data recovery the rx clock & data recovery is used to recover the clock signal from the received data. it is accomplished by an integrated digital phase locked loop (dpll). the recovered cloc k tracks the jitter in the data output from the slicer and keeps the phase relationship between data and clock during the absence of the incoming pulse. note that the idt82p2521 also provides programmable refa and refb pins to output any of the 22 recovered line clocks. refer to section 3.5 clock inputs and outputs for details. 3.1.5 decoder the decoder is used only when the receive system interface is in single rail nrz format mode. when the receive system interface is in other modes, the decoder is by passed automatically. (refer to section 3.1.6 receive system interface for the description of the receive system interface). the received signal is decoded by ami or hdb3 line code rule. the line code rule is selected by the r_code bit (b2, rcf1,...). 3.1.6 receive system interface the received data can be output to the system side in four modes: single rail nrz format mode, dual rail nrz format mode, dual rail rz format mode and dual rail sliced mode, as selected by the r_md[1:0] bits (b1~0, rcf1). if data is output on rdn in nrz format and the recovered clock is output on rclkn, the receive system interface is in single rail nrz format mode. in this mode, the data is decoded and updated on the active edge of rclkn. rclkn output s a 2.048 mhz clock. the receive multiplex function (rmfn) si gnal is updated on the active edge of rclkn and can be selected to indicate prbs/arb, lais, lexz, lbpv, lexz + lbpv, llos, output recover ed clock (rclk) or xor output of positive and negative sliced data. refer to section 3.4.7.1 rmfn indica- tion for the description of rmfn. if data is output on rdpn and rdnn in nrz format and the recov- ered clock is output on rclkn, the rece ive system interface is in dual rail nrz format mode. in this mode, the data is un-decoded and updated on the active edge of rclkn. rclkn outputs a 2.048 mhz clock. if data is output on rdpn and rdnn in rz format and the recovered clock is output on rclkn, the receiv e system interface is in dual rail rz format mode. in this mode, the data is un-decoded and updated on the active edge of rclkn. rclkn outputs a 2.048 mhz clock. if data is output on rdpn and rdnn in rz format directly after passing through the slicer, the receive system interface is in dual rail sliced mode. in this mode, the data is raw sliced and un-decoded. rmfn can be selected to indicate prbs/arb, lais, lexz, lbpv, lexz + lbpv, llos, output recovered clock (rclk) or xor output of positive and negative sliced data. refer to chapter 3.4.7.1 rmfn indication for the description of rmfn. table-2 summarizes the multiplex pin used in different receive system interface. table-2 multiplex pin used in receive system interface receive system interface multiplex pin used on receive system interface rdn / rdpn rdnn / rmfn rclkn / rmfn single rail nrz format rdn 1 rmfn 2 rclkn 3 dual rail nrz format rdpn 1 rdnn 1 rclkn 3 dual rail rz format rdpn 1 rdnn 1 rclkn 3 dual rail sliced rdpn 1 rdnn 1 rmfn 2 note: 1. the active level on rdn, rdpn and rdnn is selected by the rd_inv bit (b3, rcf1,...). 2. rmfn is always active high. 3. the active edge of rclkn is selected by the rck_es bit (b4, rcf1,...).
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 34 december 7, 2005 3.1.7 receiver power down set the r_off bit (b5, rcf0,...) to ?1? will power down the corre- sponding receiver. in this way, the corresponding receive circuit is turned off and the rtipn/rringn pins are forced to high-z state. the pins on receive system interface (including rdn/ rdpn, rdnn/rmfn, rclkn/rmfn) will be in high-z state if the rhz bit (b6, rcf0,...) is ?1? or in low level if the rhz bit (b6, rcf0,...) is ?0?. after clearing the r_off bit (b5, rcf0,...), it will take 1 ms for the receiver to achieve steady state, i.e., to return to the previous configura- tion and performance. 3.2 transmit path 3.2.1 transmit system interface the data from the system side is input to the device in three modes: single rail nrz format mode, d ual rail nrz format mode and dual rail rz format mode, as selected by the t_md[1:0] bits (b1~0, tcf1,...). if data is input on tdn in nrz form at and a 2.048 mhz clock is input on tclkn, the transmit system interface is in single rail nrz format mode. in this mode, the data is encoded and sampled on the active edge of tclkn. tmfn is updated on the active edge of tclkn and can be selected to indicate prbs/arb, sais, toc, tlos or sexz. refer to section 3.4.7.2 tmfn indication for the description of tmfn. if data is input on tdpn and tdnn in nrz format and a 2.048 mhz clock is input on tclkn, the transmit system interface is in dual rail nrz format mode. in this mode, the data is pre-encoded and sampled on the active edge of tclkn. if data is input on tdpn and tdnn in rz format and no transmit clock is input, the transmit system interface is in dual rail rz format mode. in this mode, the data is pre-encoded. tmfn can be selected to indicate prbs/arb, sais, toc, tlos, sexz, sbpv, sexz + sbpv or slos. refer to section 3.4.7.2 tmfn indication for the description of tmfn. the tx clock recovery block is used to recover the clock signal from the data input on tdpn and tdnn. refer to section 3.2.2 tx clock recovery. table-3 summarizes the multiplex pin used in different transmit system interface.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 35 december 7, 2005 3.2.2 t x clock recovery the tx clock recovery is used only when the transmit system inter- face is in dual rail rz format mode. when the transmit system inter- face is in other modes, the tx clock recovery is bypassed automatically. the tx clock recovery is used to recover the clock signal from the data input on tdpn and tdnn. 3.2.3 encoder the encoder is used only when the transmit system interface is in single rail nrz format mode. when t he transmit system interface is in other modes, the encoder is bypassed automatically. the data to be transmitted is encoded by ami or hdb3 line code rule. the line code rule is selected by the t_code bit (b2, tcf1,...). 3.2.4 waveform shaper the idt82p2521 provides two ways to manipulate the pulse shape before data is transmitted: ? preset waveform template; ? user-programmable arbitrary waveform. 3.2.4.1 preset waveform template the waveform template meets g.703, as shown in figure-15. it is measured in the near end line side, as shown in figure-16. the puls[3:0] should be set to ? 0000? if differential signals (output from ttip and tring) are coupled to a 75 ? coaxial cable using internal impedance matching mode; the puls[3:0] should be set to ?0001? for other e1 interfaces. refer to table-4 for details. figure-15 e1 waveform template figure-16 e1 waveform template measurement circuit table-3 multiplex pin used in transmit system interface transmit system interface multiplex pin used on transmit system interface tdn / tdpn tdnn / tmfn tclkn / tdnn single rail nrz format tdn 1 tmfn 2 tclkn 3 dual rail nrz format tdpn 1 tdnn 1 tclkn 3 dual rail rz format tdpn 1 tmfn 2 tdnn 1 note: 1. the active level on tdn, tdpn and tdnn is selected by the td_inv bit (b3, tcf1,...). 2. tmfn is always active high. 3. the active edge of tclkn is selected by the tck_es bit (b4, tcf1,...). if tclkn is missing, i.e., no transition for more than 64 e1 clock cycles, the tcklos_s bit (b3, stat0,...) will be set. a transit ion from ?0? to ?1? on the tc klos_s bit (b3, stat0,...) or any transition (from ?0? to ?1? or from ?1? to ?0?) on the tcklos_s bit (b3, stat0,...) will set the tcklos_is bit (b3, ints0,...) to ?1 ?, as selected by the tcklos_ies bit (b3, intes,...). when the tcklos_is bit (b3, ints0, ...) is ?1?, an interr upt will be reported by int if not masked by the tcklos_im bit (b3, intm0,...). -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 normalized amplitude time in unit intervals idt82p2821 v out r load ttipn tringn note: r load = 75 ? or 120 ? (+ 5%) idt82p2821 v out r load ttipn tringn note: r load = 75 ? or 120 ? (+ 5%)
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 36 december 7, 2005 after one of the preset waveform templates is selected, the preset waveform amplitude can be adjusted to get the desired waveform. the scal[5:0] bits (b5~0, scal,...) should be set to ?100001? to get the standard amplitude. the adjus ting is made by increasing or decreasing by ?1? from the standard value to scale up or down at a percentage ratio of 3%. in summary, do the following step by step, the desired waveform will be got based on the preset waveform template: ? select one preset waveform template by setting the puls[3:0] bits (b3~0, puls,...); ? write ?100001 to the scal[5:0] bits (b5~0, scal,...). ? write the scaling value to the scal[5:0] bits (b5~0, scal,...) to scale the amplitude of the selected preset waveform template (- this step is optional). 3.2.4.2 user-programmable arbitrary waveform when the puls[3:0] bits (b3~0, puls,...) are set to ?1xxx?, user- programmable arbitrary waveform will be used in the corresponding channel. each waveform shape can extend up to uis (unit interval), and is divided into 20 sub-phases that ar e addressed by the samp[4:0] bits (b4~0, awg0,...). the waveform am plitude of each phase is repre- sented by a binary byte, within the range from +63 to -63, stored in the wdat[6:0] bits (b6~0, awg1,...) in signed magnitude form. the maximum number +63 (d) represent s the maximum positive amplitude of the transmit pulse while the mo st negative number -63 (d) represents the maximum negative amplitude of the transmit pulse. therefore, up to 20 bytes are used. there are eight standard templates which are stored in a local rom. one of them can be selected as reference and made some changes to get the desired waveform. to do this, the first step is to choose a set of waveform value from the standard templates. the selected waveform value should be the most similar to the desired waveform shape. table-5 and table-6 list the sample data of each template. then modify the sample data to get the desired transmit waveform shape. by increasing or decreasing by ?1? from the standard value in the scal[5:0] bits (b5~0, scal,...), t he waveform amplitude will be scaled up or down. in summary, do the following for the write operation: ? modify the sample data in the awg1 register; ? write the awg0 register to im plement the write operation, includ- ing: - write the sample address to the samp[4:0] bits (b4~0, awg0,...); - write ?0? to the rw bit (b5, awg0,...); - write ?1? to the done bit (b6, awg0,...). do the following for the read operation: ? write the awg0 register, including: - write sample address to the samp[4:0] bits (b4~0, awg0,...); - write ?1? to the rw bit (b5, awg0,...); - write ?1? to the done bit (b6, awg0,...); ? read the awg1 register to get the sample data. when the write operation is completed, write the scaling value to the scal[5:0] bits (b5~0, scal,...) to scale the amplitude of the selected standard waveform (- this step is optional). when more than one ui is used to compose the waveform template and the waveform amplitude is not set properly, the overlap of the two consecutive waveforms will make the waveform amplitude overflow (i.e., exceed the maximum limitation). this overflow is captured by the dac_is bit (b7, ints0,...) and will be reported by the int pin if enabled by the dac_im bit (b7, intm0,...). table-4 puls[3:0] setting interface conditions puls[3:0] e1 75 ? differential interface, internal impedance matching mode 0000 other e1 interface 0001 1 1 4 -- -
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 37 december 7, 2005 refer to application note an-513 ?user-programmable arbitrary waveform for dsx1? for more details. table-5 transmit waveform value for e1 75 ohm samp[4:0] 1234567891011121314151617181920 wdat[6:0] 00h 00h 00h 0ch 30h 30h 30h 30h 30h 30h 30h 30h 00h 00h 00h 00h 00h 00h 00h 00h table-6 transmit waveform value for e1 120 ohm samp[4:0] 1234567891011121314151617181920 wdat[6:0] 00h 00h 00h 0fh 3ch 3ch 3ch 3ch 3ch 3ch 3ch 3ch 00h 00h 00h 00h 00h 00h 00h 00h
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 38 december 7, 2005 3.2.5 line driver the line driver can be set to hi gh-z for protection or in redundant applications. the following two ways will se t the line driver to high-z: ? setting the oe pin to low will globally set all the line drivers to high-z; ? setting the oe bit (b6, tcf0,...) to ?0? will set the corresponding line driver to high-z. by these ways, the functionality of t he internal circuit is not affected and ttipn and tringn will ent er high-z state immediately. 3.2.5.1 transmit over current protection the line driver monitors the tr ansmit over current (toc) on the line interface. when toc is detected, the driver?s output (i.e., output on ttipn/tringn) is determined by t he thz_oc bit (b4, tcf0,...). if the thz_oc bit (b4, tcf0,...) is ?0?, the driver?s output current (peak to peak) is limited to 100 ma; if the thz_ oc bit (b4, tcf0,...) is ?1?, the driver?s output will enter high-z. to c is indicated by the toc_s bit (b4, stat0,...). a transition from ?0? to ?1? on the toc_s bit (b4, stat0,...) or any transition (from ?0? to ?1? or fr om ?1? to ?0?) on the toc_s bit (b4, stat0,...) will set the toc_is bit (b4, ints0,...) to ?1?, as selected by the toc_ies bit (b4, intes ,...). when the toc_is bit (b4, ints0,...) is ?1?, an interrupt will be reported by int if not masked by the toc_im bit (b4, intm0,...). toc may be indicated by the tmfn pin. refer to section 3.4.7.2 tmfn indication for details. 3.2.6 t x termination the transmit line interface supports transmit differential mode and transmit single ended mode, as se lected by the t_sing bit (b3, tcf0,...). in transmit di fferential mode, both ttipn and tringn are used to transmit signals to the line side. in transmit single ended mode, only ttipn is used to transmit signal. the line interface can be connected with e1 120 ? twisted pair cable or e1 75 ? coaxial cable. the transmit impedance matching is realized by using internal impedance matching or external impedance matching for each channel in different applications. 3.2.6.1 transmit differential mode in transmit differential mode, di fferent applications have different impedance matching. for e1 applicat ions, both internal and external impedance matching are supported. internal impedance matching circuit uses an internal programmable resistor (im) only. external impedance matching circuit uses an external resistor (rt) only. a twisted pair cable can be connect ed with a 1:2 (step up) trans- former or without a transformer (tr ansformer-less), while a coaxial cable must be connected with a 1:2 transformer. the t_term[2:0] bits (b2~0, tc f0,...) should be set according to different cable conditions, whether a transformer is used, and what kind of impedance matching is selected. table-7 lists the recomm ended impedance matching value in different applications. figure-17 to figure-19 show the connection for one channel in different applications. the transformer-less connection will offer a termination option with reduced cost and board space. however, the waveform amplitude is not standard compliant, and surge pr otection and common mode depres- sion should be enhanced depending on equipment environment.. table-7 impedance matching value in transmit differential mode cable condition internal impedance matching external impedance matching t_term[2:0] rt t_term[2:0] rt e1 120 ? twisted pair (with transformer), puls[3:0]=0001 010 0 111 10 ? e1 75 ? coaxial (with transformer), puls[3:0]=0000 011 e1 120 ? twisted pair (transformer-less), puls[3:0]=0001 110 (not supported)
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 39 december 7, 2005 figure-17 transmit differential line interface with twisted pair cable (with transformer) figure-18 transmit differential line interface with co- axial cable (wit h transformer) figure-19 transmit differential line interface with twisted pair cable (transformer-less, non standard compliant) 3.2.6.2 transmit single ended mode transmit single ended mode can only be used in 75 ? coaxial cable applications. in transmit single ended mode, onl y internal impedance matching is supported. internal impedance matc hing circuit uses an internal programmable resistor (im) only. t he t_term[2:0] bits (b2~0, tcf0,...) should be set to ?011?. the output amplitude is 4.74 vpp when puls[3:0] is ?0001? and the scal[5:0] bits (b5~0, scal,...) is ?100001?. 1 in single ended mode, special care has to be taken for termination and overall setup. refer to separate application note for details. a 1:2 (step up) transformer should be used in application. figure-20 shows the connection for one channel. figure-20 transmit single ended line interface with coaxial cable (with transformer) 1:2 rt ttipn tringn im 6.0 vpp rt 1:2 rt ttipn tringn im 4.74 vpp rt ttipn tringn im 3.0vpp in this mode, port protection should be enhanced. note: 1. the waveform in this mode is not standard. however, if the arbitrary wave- form generator is used, the waveform could pass the template marginally. 1:2 ttipn tringn im 4.74 vpp 4.7 f
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 40 december 7, 2005 3.2.7 transmitter power down set the t_off bit (b5, tcf0,...) to ?1? will power down the corre- sponding transmitter. in this way, the corresponding transmit circuit is turned off. the pins on the transmit line interface (inc luding ttipn and tringn) will be in high-z state. the input on the trans mit system interface (including tdn, tdpn, tdnn and tclk) is ignored. the output on the transmit system interface (i.e. tmfn) will be in high-z state. after clearing the t_off bit (b5, tc f0,...), it will take 1 ms for the transmitter to achieve steady state, i.e ., return to the previous configura- tion and performance. 3.2.8 output high-z on ttip and tring ttipn and tringn can be set to hi gh-z state globally or on a per- channel basis. the following three conditions will set ttipn and tringn to high-z state globally: ? connecting the oe pin to low; ? loss of mclk (i.e., no transition on mclk for more than 1 ms); ? power on reset, hardware reset by pulling rst to low for more than 2 s or global software rese t by writing the rst register. the following six condi tions will set ttipn and tringn to high-z state on a per-channel basis: ? writing ?0? to the oe bit (b6, tcf0,...); ? loss of tclkn in transmit single rail nrz format mode or transmit dual rail nrz format mode (i.e., no transition on tclkn for more than 64 xclk 1 cycles) except that the channel is in remote loopback or transmit internal pattern with xclk; ? transmitter power down; ? per-channel software reset by writing ?1? to the chrst bit (b1, chcf,...); ? setting the thz_oc bit (b4, tc f0,...) to ?1? when transmit driver over-current is detected. 1. xclk is derived from mclk. it is 2.048 mhz .
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 41 december 7, 2005 3.3 jitter attenuator (rja & tja) two jitter attenuators are provi ded for each channel of receiver and transmitter. each jitter attenuator can be enabled or disabled, as deter- mined by the rja_en/tja_en bit ( b3, rja/tja,...) respectively. each jitter attenuator consists of a fifo and a dpll, as shown in figure-21. figure-21 jitter attenuator the fifo is used as a pool to buffer the jittered input data, then the data is clocked out of the fifo by a de-jittered clock. the depth of the fifo can be 32 bits, 64 bits or 128 bi ts, as selected by the rja_dp[1:0]/ tja_dp[1:0] bits (b2~1, rja/tja ,...). accordingly, the typical delay produced by the jitter attenuator is 16 bits, 32 bits or 64 bits. the 128- bit fifo is used when large jitter tole rance is expected, while the 32-bit fifo is used in delay sensitive applications. the dpll is used to generate a de-jitte red clock to clock out the data stored in the fifo. the dpll can only attenuate the incoming jitter whose frequency is above corner fr equency (cf) by 20 db per decade falling off. the jitter whose frequen cy is lower than the cf passes through the dpll without any attenuation. the cf of the dpll is 6.77 hz or 0.87 hz. the cf is sele cted by the rja_bw/tja_bw bit (b0, rja/tja,...). the lower the cf is, the longer time is needed to achieve synchronization. if the incoming data moves faster than the outgoing data, the fifo will overflow. if the incoming data moves slower than the outgoing data, the fifo will underflow. the overfl ow and underflow are both captured by the rja_is/tja_is bit (b5/6, in ts0,...). the occurrence of overflow or underflow will be reported by the int pin if enabled by the rja_im/ tja_im bit (b5/6, intm0,...). to avoid overflow or underflow, the ja-limit function can be enabled by setting the rja_limt/tja_limt bi t (b4, rja/tja,...). when the ja- limit function is enabled, the speed of the outgoing data will be adjusted automatically if the fifo is 2-bit close to its full or emptiness. though the ja-limit function can reduce t he possibility of fifo overflow and underflow, the quality of jitter attenuation is deteriorated. the performance of the jitter attenuator meets itut i.431, g.703, g.736-739, g.823, g.824, etsi 300011, etsi tbr12/13, at&t tr62411, tr43802, tr-tsy 009, tr -tsy 253 and tr-try 499. refer to section 8.10 jitter attenuation ch aracteristics for the jitter perfor- mance. fifo 32/64/128 dpll jittered data de-jittered data jittered clock de-jittered clock write clock read clock
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 42 december 7, 2005 3.4 diagnostic facilities the diagnostic facilities include: ? bpv (bipolar violation) / cv (code violation) detection and bpv insertion; ? exz (excessive zero) detection; ? los (loss of signal) detection; ? ais (alarm indication signal) detection and generation; ? pattern generation and detection, including prbs (pseudo ran- dom bit sequence), arb (arbitrary pattern) and ib (inband loop- back). the above defects, alarms or patterns can be counted by an internal error counter, indicated by the respec tive interrupt bit and indicated by rmfn or tmfn. for diagnostic purposes, loopbacks and channel 0 monitoring can also be implemented. 3.4.1 bipolar violation (bpv) / code violation (cv) detection and bpv insertion 3.4.1.1 bipolar violation (bpv) / code violation (cv) detection bpv/cv is monitored in both the receive path and the transmit path. bpv is detected when the data is ami coded and cv is detected when the data is hdb3 coded. if the transmi t system interface is in transmit single rail nrz format mode, the bpv/cv detection is disabled in the transmit path automatically. a bpv is detected when two consecut ive pulses of the same polarity are received. a cv is detected when two consecut ive bpvs of the same polarity that are not a part of the hdb3 zero substitution are received. when bpv/cv is detected in the receive path, the line bipolar viola- tion lbpv_is bit (b4, ints2,...) w ill be set and an interrupt will be reported by int if not masked by the lbpv_im bit (b4, intm2,...). when bpv/cv is detected in the transmit path, the system bipolar violation sbpv_is bit (b5, ints2,...) will be set and an interrupt will be reported by int if not masked by the sbpv_im bit (b5, intm2,...). bpv/cv may be counted by an internal error counter or may be indi- cated by the rmfn or tmfn pin. refer to section 3.4.6 error counter and section 3.4.7 receive /transmit multiplex function (rmf / tmf) indication respectively. 3.4.1.2 bipolar violation (bpv) insertion the bpv can only be inserted in the transmit path. a bpv will be inserted on the next av ailable mark in the data stream to be transmitted by writing a ?1? to the bpv_ins bit (b6, err,...). this bit will be reset once bpv insertion is done. 3.4.2 excessive zeroes (exz) detection exz is monitored in both the receive path and the transmit path. different line code has different definition of the exz. the idt82p2521 provides two standards of exz definition for each kind of line code rule. the standards are ansi and fcc, as selected by the exz_def bit (b7, err,...). refer to table-8 for details. when exz is detected in the receive path, the lexz_is bit (b2, ints2,...) will be set and an in terrupt will be reported by int if not masked by the lexz_im bit (b2, intm2,...). when exz is detected in the tr ansmit path, the sexz_is bit (b3, ints2,...) will be set and an in terrupt will be reported by int if not masked by the sexz_im bit (b3, intm2,...). exz may be counted by an internal error counter or may be indi- cated by the rmfn or tmfn pin. refer to chapter 3.4.6 error counter and chapter 3.4.7 receive /transmit multiplex function (rmf / tmf) indication respectively. table-8 exz definition line code rule definition ansi (exz_def = 0) fcc (exz_def = 1) ami an exz is detected when any string of more than 15 consecutive ?0?s are received. an exz is detected when any string of more than 15 consecutive ?0?s are received. hdb3 an exz is detected when any string of more than 3 consecutive ?0?s are received. an exz is detected when any string of more than 3 consecutive ?0?s are received. note: if the transmit system interface is in tr ansmit single rail nrz format mode, the exz is detected according to the standard of ami.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 43 december 7, 2005 3.4.3 loss of signal (los) detection the idt82p2521 detects three kinds of los: ? llos: line los, detected in the receive path; ? slos: system los, detected in the transmit system side; ? tlos: transmit los, detected in the transmit line side. 3.4.3.1 line los (llos) the amplitude and density of the dat a received from the line side are monitored. when the amplitude of the data is less than q vpp for n consecutive pulse intervals, llos is declared. when the amplitude of the data is more than p vpp and the average density of marks is at least 12.5% for m consecutive pulse interv als starting with a mark, llos is cleared. here q is defined by the alos[2:0] bits (b6~4, los,...). p is the sum of q and 250 mvpp. n and m are defined by the lac bit (b7, los,...). refer to table-9 for details. llos detection supports g.775 and etsi 300233/i.431. the criteria are selected by the lac bit (b7, los,...). when llos is detected, the llos_s bit (b0, stat0,...) will be set. a transition from ?0? to ?1? on the llos_ s bit (b0, stat0,...) or any transi- tion (from ?0? to ?1? or from ?1? to ?0?) on the llos_s bit (b0, stat0,...) will set the llos_is bit (b0, ints0,...) to ?1?, as selected by the los_ies bit (b1, intes,...). when the llos_is bit (b0, ints0,...) is ?1?, an interrupt will be reported by int if not masked by the llos_im bit (b0, intm0,...). two pins (llos0 and llos) are dedicated to llos indication. whether llos is detected in channel 0 or not, llos0 is high for a clke1 clock cycle to indicate the channel 0 position on llos. llos indicates llos status of all 22 c hannels in a serial format and repeats every 22 cycles. refer to figure-22. llos0 and llos are updated on the rising edge of clke1. when the clock output on clke1 is disabled, llos0 and llos will be held in high-z state. the output on clke1 is controlled by the clke1_en bit (b3, clkg) and the clke1 bit (b2, clkg). refer to section 8.9 on page 129 for clke1 timing characteris- tics. llos may be counted by an internal error counter or may be indi- cated by the rmfn pin. refer to section 3.4.6 error counter and section 3.4.7.1 rmfn indication respectively. during llos, in receive single rail nrz format mode, receive dual rail nrz format mode and rece ive dual rail rz format mode, rdn and rdpn/rdnn output low level. in receive dual rail sliced mode rdpn/rdnn still output sliced dat a. rclkn (if available) outputs high level or xclk 1 , as selected by the rckh bit (b7, rcf0,...). during llos, if any of ais, pattern generation in the receive path or digital loopback is enabled, rdn, rdpn/rdnn and rclkn output corresponding data and clock, and the setting of the rckh bit (b7, rcf0,...) is ignored. refer to the corresponding chapters for details. figure-22 llos indication on pins 1. xclk is derived from mclk. it is 2.048 mhz . table-9 llos criteria operation mode lac criteria llos declaring llos clearing e1 0 g.775 below q vpp, n = 32 bits above p vpp, 12.5% mark density with less than 16 consecutive zeros, m = 32 bits 1 etsi 300233/ i.431 below q vpp, n = 2048 bits above p vpp, 12.5% mark density with less than 16 consecutive zeros, m = 32 bits one llos indication cycle llos llos0 clke1 ch0 ch1 ch2 ch21 ch0 012 21 0
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 44 december 7, 2005 3.4.3.2 system los (slos) slos can only be detected when the transmit system interface is in dual rail nrz format mode or in dual rail rz format mode. the amplitude and density of the dat a input from the transmit system side are monitored. when the input ?0?s are equal to or more than n consecutive pulse intervals, sl os is declared. when the average density of marks is at least 12.5% for m consecutive pulse intervals starting with a mark, slos is cleared. here n and m are defined by the lac bit (b7, los,...). refer to table-10 for details. slos detection supports g.775 and etsi 300233/i.431. the criteria are selected by the lac bit (b7, los,...). when slos is detected, the slos_s bit (b1, stat0,...) will be set. a transition from ?0? to ?1? on the slos _s bit (b1, stat0,...) or any transi- tion (from ?0? to ?1? or from ?1? to ?0?) on the slos_s bit (b1, stat0,...) will set the slos_is bit (b1, ints0,...) to ?1?, as selected by the los_ies bit (b1, intes,...). when the slos_is bit (b1, ints0,...) is ?1?, an interrupt will be reported by int if not masked by the slos_im bit (b1, intm0,...). slos may be counted by an internal error counter or may be indi- cated by the tmfn pin. refer to section 3.4.6 error counter and section 3.4.7.2 tmfn indication respectively. table-10 slos criteria operation mode lac criteria slos declaring 1 slos clearing 1 e1 0 g.775 no pulse detected for n consecutive pulse intervals, n = 32 bits 12.5% mark density with less than 16 consecutive zeros for m consecutive pulse intervals, m = 32 bits 1 etsi 300233/ i.431 no pulse detected for n consecutive pulse intervals, n = 2048 bits 12.5% mark density with less than 16 consecutive zeros for m consecutive pulse intervals, m = 32 bits note: 1. system input ports ar e schmitt-trigger inputs)
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 45 december 7, 2005 3.4.3.3 transmit los (tlos) the amplitude and density of the dat a output on the transmit line side are monitored. when the amplitude of the data is less than a certain voltage for a certain period, tlos is declared. the voltage is defined by the talos[1:0] bits (b3~2, los ,...). the period is defined by the tdlos[1:0] bits (b1~0, los,...). when a valid pulse is detected, i.e., the amplitude is above the setting in the talos[1:0] bits (b3~2, los,...), tlos is cleared. when tlos is detected, the tlos_s bit (b2, stat0,...) will be set. a transition from ?0? to ?1? on the tlos _s bit (b2, stat0,...) or any transi- tion (from ?0? to ?1? or from ?1? to ?0 ?) on the tlos_s bit (b2, stat0,...) will set the tlos_is bit (b2, ints0,...) to ?1?, as selected by the tlos_ies bit (b2, intes,...). when the tlos_is bi t (b2, ints0,...) is ?1?, an inter- rupt will be reported by int if not masked by the tlos_im bit (b2, intm0,...). tlos may be counted by an internal error counter or may be indi- cated by the tmfn pin. refer to section 3.4.6 error counter and section 3.4.7.2 tmfn indication respectively. tlos can be used to monitor the los in the transmit line side between two channels. the connec tion between the two channels is shown in figure-23. the two channels can be of the same device or different devices on the premises that the transmit line interfaces are in the same mode and at least the output of one channel is in high-z state. table-11 lists each results in this case. in the left two columns, the oe bit (b6, tcf0,...) of the two channels c ontrols the output status in the transmit line side to ensure that at least one channel is in high-z state. the middle two columns list the intern al operation status. in the right two columns, the tlos_s bit (b2, stat 0,...) of the two channels indicates the tlos status in the transmit line side. figure-23 tlos detection between two channels line driver tlos line driver tlos ttipn tringn ttipn tringn channel #1 channel #2 tlos detector tlos detector table-11 tlos detection between two channels output status ~ controlled by the oe bit internal oper ation status tlos status ~ indicated by the tlos_s bit channel #1 channel #2 channel #1 channel #2 channel #1 channel #2 normal ~ 1 high-z ~ 0 normal (don?t-care) no tlos ~ 0 no tlos ~ 0 normal ~ 1 high-z ~ 0 failure normal tlos detected ~ 1 * tlos detected ~ 1 high-z ~ 0 normal ~ 1 (don?t-care) normal no tlos ~ 0 no tlos ~ 0 high-z ~ 0 normal ~ 1 normal failure tlos detected ~ 1 tlos detected ~ 1 * high-z ~ 0 high-z ~ 0 (don?t-care) (don?t-care) tlos detected ~ 1 tlos detected ~ 1 note: * the tlos_s bit (b2, stat0,...) may not be set if there is any catastrophic failure in the channel.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 46 december 7, 2005 3.4.4 alarm indication signal (ais) detection and gen- eration 3.4.4.1 alarm indication signal (ais) detection ais is monitored in both the receive path and the transmit path. when the mark density in the received data or in the data input from the transmit system side meets cert ain criteria, ais is declared or cleared. in e1 mode, the criteria are in compliance with itu g.775 or etsi 300233, as selected by the lac bit (b7, los,...). refer to table-12 for details. when ais is detected in the receive path, the lais_s bit (b6, stat1,...) will be set. a transition from ?0? to ?1? on the lais_s bit (b6, stat1,...) or any transition (from ?0? to ?1? or from ?1? to ?0?) on the lais_s bit (b6, stat1,...) will set the lais _is bit (b6, ints1,...) to ?1?, as selected by the ais_ies bit (b6, intes,...). when the lais_is bit (b6, ints1,...) is ?1?, an interrupt will be reported by int if not masked by the lais_im bit (b6, intm1,...). when ais is detected in the transmit path, the sais_s bit (b7, stat1,...) will be set. a transition from ?0? to ?1? on the sais_s bit (b7, stat1,...) or any transition (from ?0? to ?1? or from ?1? to ?0?) on the sais_s bit (b7, stat1,...) will set the sais_is bit (b7, ints1,...) to ?1?, as selected by the ais_ies bit (b6, intes,...). when the sais_is bit (b7, ints1,...) is ?1?, an interrupt will be reported by int if not masked by the sais_im bit (b7, intm1,...). ais may be counted by an internal error counter or may be indicated by the rmfn or tmfn pin. refer to section 3.4.6 error counter and section 3.4.7 receive /transmit mult iplex function (rmf / tmf) indica- tion respectively. 3.4.4.2 (alarm indication signal) ais generation ais can be generated automatically in the receive path and the transmit path. in the receive path, when the asais_llos bit (b2, aisg,...) is set, ais will be generated automatically once llos is detected. when the asais_slos bit (b3, aisg,...) is set, ais will be generated automati- cally once slos is detected. w hen ais is generated, rdn or rdpn/ rdnn output all ?1?s. rclkn (if available) outputs xclk. in the transmit path, when the alais_llos bit (b0, aisg,...) is set, ais will be generated automatically once llos is detected. when the alais_slos bit (b1, aisg,...) is set, ais will be generated automati- cally once slos is detected. when ais is generated, ttipn/tringn output all ?1?s. ais generation uses xclk 1 as reference clock. if pattern (including prbs, arb and ib) is generated in the same direction, the priority of patte rn generation is higher. the generated pattern will overwrite automatic ais. refer to section 3.4.5.1 pattern generation for the output data and clock. table-12 ais criteria itu g.775 for e1 (lac = 0) etsi 300233 for e1 (lac = 1) ais declaring less than 3 zeros are received in each of two consecutive 512-bit data streams. less than 3 zeros are received in a 512-bit data stream. ais clearing 3 or more zeros are received in each of two consecutive 512-bit data streams. 3 or more zeros are received in a 512-bit data stream. 1. xclk is derived from mclk. it is 2.048 mhz .
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 47 december 7, 2005 3.4.5 prbs, qrss, arb and ib pattern generation and detection the pattern includes: pseudo random bit sequence (prbs), quasi- random signal source (qrss), arbitrary pattern (arb) and inband loopback (ib). 3.4.5.1 pattern generation the pattern can be generated in the receive path or the transmit path, as selected by the pg_pos bit (b3, pg,...). the pattern to be generated is selected by the pg_en[1:0] bits (b5~4, pg,...). if prbs is selected, three kinds of prbs patterns with maximum zero restriction according to itu-t o.151 and at&t tr62411 are provided. they are: (2^20 - 1) qr ss per o.150-4.5, (2^15 - 1) prbs per o.152 and (2^11 - 1) prbs per o.150, as selected by the prbg_sel[1:0] bits (b1~0, pg,...). if arb is selected, the content is programmed in the arb[23:0] bits (b7~0, arbh~arbm~arbl,...). if ib is selected, the ib generation is in compliance with ansi t1.403. the length of the ib code can be 3 to 8 bits, as determined by the ibgl[1:0] bits (b5~4, ibl,...). the content is programmed in the ibg[7:0] bits (b7~0, ibg,...). the selected pattern is transmitted repeatedly until the pg_en[1:0] bits (b5~4, pg,...) is set to ?00?. when pattern is generated in the receive path, the reference clock is xclk or the recovered clock from the received signal, as selected by the pg_ck bit (b6, pg,...). the selected reference clock is also output on rclkn (if available). when pattern is generated in the tr ansmit path, the reference clock is xclk 1 or the transmit clock, as selected by the pg_ck bit (b6, pg,...). the transmit clock refers to the cl ock input on tclkn (in transmit single rail nrz format mode and in transmi t dual rail nrz format mode) or the clock recovered from the data input on tdpn and tdnn (in transmit dual rail rz format mode). in summary, do the followings step by step to generate pattern: ? select the generation direction by the pg_pos bit (b3, pg,...); ? select the reference clock by the pg_ck bit (b6, pg,...); ? select the prbs pattern by the prbg_sel[1:0] bits (b1~0, pg,...) when prbs is to be generated; program the arb pattern in the arb[23:0] bits (b7~0, arbh~a rbm~arbl,...) when arb is to be generated; or set the length and the content of the ib code in the ibgl[1:0] bits (b5~4, ibl,...) and in the ibg[7:0] bits (b7~0, ibg,...) respectively when ib is to be generated; ? set the pg_en[1:0] bits (b5~4, pg,...) to generate the pattern. if prbs or arb is selected to be generated, the following two steps can be optionally implemented after the pattern is generated: ? insert a single bit error by writ ing ?1? to the err_ins bit (b5, err ,...) ; ? invert the generated pattern by setting the pag_inv bit (b2, pg ,...). if pattern is generated in the receive path, the generated pattern should be encoded by using ami hdb3 in receive dual rail nrz format mode, receive dual rail rz format mode and receive dual rail sliced mode. the encoding rule is selected by the r_code bit (b2, rcf1,...). if pattern is generated in the transmit path, the generated pattern should be encoded by using ami hdb3 . the encoding rule is selected by the t_code bit (b2, tcf1,...). the pattern generation is s hown in figure-24 and figure-25. figure-24 pattern generation (1) figure-25 pattern generation (2) the priority of pattern generation is higher than that of ais genera- tion. if they are generated in the same direction, the generated pattern will overwrite the generated ais. 1. xclk is derived from mclk. it is 2.048 mhz . prbs/arb/ib pattern generator pg_pos chn tdpn/tdnn/tclkn rdpn/rdnn/rclkn ttipn/tringn rtipn/rringn xclk pg_en[1:0] tclk/rclk pg_ck prbs generation 2^11-1 2^15-1 2^20-1 invert err_ins pag_inv single bit error insert 24 bits arb arb[23:0] pg_en[1:0] prbg_sel[1:0]
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 48 december 7, 2005 3.4.5.2 pattern detection data received from the line side or data input from the transmit system side may be extracted for pattern detection. the direction of data extraction is determined by the pd_p os bit (b3, pd,...). one of prbs or arb pattern is selected for detection and ib detection is always active. if data is extracted from the receive path, before pattern detection the data should be decoded by using ami / hdb3. the decoding rule is selected by the r_code bit (b2, rcf1,...). if data is extracted from the transmit path, before pattern detection the data should be decoded by using ami hdb3 in transmit dual rail nrz format mode and transmit dual rail rz format mode. the decoding rule is selected by the t_code bit (b2, tcf1,...). pseudo random bit sequence (p rbs) /arbitrary pattern (arb) detection the extracted data can be optionally inverted by the pad_inv bit (b2, pd,...) before prbs/arb detection. the extracted data is used to compare with the desired pattern. the desired pattern is re-generated from the extracted data if the desired pattern is (2^20 - 1) qrss per o.150-4.5, (2^15 - 1) prbs per o.152 or (2^11 - 1) prbs per o.150; or the desired pattern is programmed in the arb[23:0] bits (b7~0, arbh~arbm~ arbl,...) if the desired pattern is arb. the desired pattern is selected by the pad_sel[1:0] bits (b1~0, pd,...). in summary, do the followings step by step to detect prbs/arb: ? select the detection direction by the pd_pos bit (b3, pd,...); ? set the arb[23:0] bits (b7~0, arbh~arbm~arbl,...) if the arb pattern is desired - this step is omitted if the prbs pattern is desired; ? select the desired prbs/arb pattern by the pad_sel[1:0] bits (b1~0, pd,...). the priority of decoding, data inve rsion, pattern re-generation, bit programming and pattern comparis on is shown in figure-26. figure-26 prbs / arb detection during comparison, if the extract ed data coincides with the re-gener- ated prbs pattern or the programmed arb pattern for more than 64-bit hopping window, the pattern is sync hronized and the pa_s bit (b5, stat1,...) will be set. in synchronization state, if more than 6 prbs/arb errors are detected in a 64-bit hopping window, the pattern is out of synchroniza- tion and the pa_s bit (b5, stat1,...) will be cleared. in synchronization state, each mi smatched bit will generate a prbs/ arb error. when a prbs/arb error is detected during the synchroniza- tion, the err_is bit (b1, ints2,...) will be set and an interrupt will be reported by int if not masked by the err_im bit (b1, intm2,...). the prbs/arb error may be counted by an internal error counter. refer to section 3.4.6 error counter. a transition from ?0? to ?1? on the pa _s bit (b5, stat1,...) or any tran- sition (from ?0? to ?1? or from ?1? to ?0?) on the pa_s bit (b5, stat1,...) will set the pa_is bit (b5, ints1,...) to ?1?, as selected by the pa_ies bit (b5, intes,...). when the pa_is bit (b5, ints 1,...) is ?1?, an interrupt will be reported by int if not masked by the pa_im bit (b5, intm1,...). the prbs/arb synchronization status may be indicated by the rmfn or tmfn pin. refer to section 3.4.7 receive /transmit multiplex function (rmf / tmf) indication. from rx path or tx path decoding data inversion prbs re- generation comparison arb[23:0] programming
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 49 december 7, 2005 inband loopback (ib) detection the ib detection is in compliance with ansi t1.403. the extracted data is used to compare with the target ib code. the length of the target activate/deactivate ib code can be 3 to 8 bits, as determined by the ibal[1:0]/ibdl[1:0] bits (b3~2/b1~0, ibl,...). the content of the target activate/deacti vate ib code is programmed in the iba[7:0]/ibd[7:0] bits (b7~0, ibda/ibdd,...). refer to figure-27. figure-27 ib detection during comparison, if the extrac ted data coincides with the target activate/deactivate ib code with no more than 10 -2 bit error rate for a certain period, the ib code is detected. the period depends on the setting of the autolp bit (b3, loop,...). if the autolp bit (b3, loop,...) is ?0?, automatic digital/remote loopback is disabled. in this case, when the activate ib code is detected for more than 40 ms, the iba_s bit (b1, stat1,...) will be set to indicate the activate ib code detection; when the deactivate ib code is detected for more than 30 ms, the ibd_s bit (b0, stat1,...) will be set to indicate the deactivate ib code detection. if the autolp bit (b3, loop,...) is ?1?, automatic digital/remote loopback is enabled. in this case, when the activate ib code is detected for more than 5.1 seconds, the iba_s bit (b1, stat1,...) will be set to indicate the activate ib code detecti on. the detection of the activate ib code in the receive path will activate remote loopback or the detection of the activate ib code in the trans mit path will activate digital loopback (refer to section 3.4.8.2 remote loopback & section 3.4.8.3 digital loopback). when the deactivate ib code is detected for more than 5.1 seconds, the ibd_s bit (b0, stat1,...) will be set to indicate the deacti- vate ib code detection. the detection of the deactivate ib code in the receive path will deactivate remote loopback or the detection of the deactivate ib code in the transmit path will deactivate digital loopback (refer to section 3.4.8.2 remote loopback & section 3.4.8.3 digital loopback). a transition from ?0? to ?1? on the iba_s/ibd_s bit (b1/b0, stat1,...) or any transition (from ?0? to ?1? or from ?1? to ?0?) on the iba_s/ibd_s bit (b1/b0, stat1,...) will set the iba_is/ibd_is bit (b1/b0, ints1,...) to ?1? respectively, as selected by the ib_ies bit (b0, intes,...). when the iba_is/ibd_is bit (b1/b0, ints1,...) is ?1?, an interrupt will be reported on int if not masked by the iba_im/ibd_im bit (b1/b0, intm1,...). 3.4.6 error counter an internal 16-bit error counter is used to count one of the following errors: ? lbpv: bpv/cv detected in the receive path (line side); ? lexz: exz detected in the receive path (line side); ? lbpv + lexz: bpv/cv and exz detected in the receive path (line side); ? sbpv: bpv/cv detected in the transmit path (system side) (dis- abled in transmit single rail nrz format mode); ? sexz: exz detected in the transmit path (system side); ? sbpv + sexz: bpv/cv and exz detected in the transmit path (system side) (disabled in tr ansmit single rail nrz format mode); ? prbs/arb error. the cnt_sel[2:0] bits (b4~2, err,...) select one of the above errors to be counted. the error counter is buffered. it is updated automatically or manu- ally, as determined by the cnt_md bit (b1, err,...). the error counter is accessed by reading the errch and errcl registers. 3.4.6.1 automatic error counter updating when the cnt_md bit (b1, err,...) is ?1?, the error counter is updated every one second automatically. the one-second timer uses mclk as clock reference. the expiration of each one second will set the tmov _is bit (b0, inttm) and induce an interrupt reported by int if not masked by the tmov_im bit (b0, gcf). when each one second expires, the error counter transfers the accumulated error numbers to the errch and errcl registers and the error counter will be cleared to start a new round counting. the errch and errcl registers should be read in the next second, other- wise they will be overwritten. when the errch and errcl registers are all ?1?s and there is still error to be accumulated, the register s will be overflowed. the overflow is indicated by the cntov_is bit (b0, ints2,...) and will induce an inter- rupt reported by int if not masked by the cntov_im (b0, intm2,...). the process of automatic error counter updating is illustrated in figure-28. from rx path or tx path decoding target code - length & content programming comparison
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 50 december 7, 2005 figure-28 automatic error counter updating 3.4.6.2 manual error counter updating when the cnt_md bit (b1, err,...) is ?0?, the error counter is updated manually. when there is a transition from ?0? to ?1? on the cnt_stop bit (b0, err,...), the error counter transfers the accumulated error numbers to the errch and errcl registers and t he error counter will be cleared to start a new round counting. t he errch and errcl registers should be read in the next round of error counting, otherwise they will be over- written. when the errch and errcl registers are all ?1?s and there is still error to be accumulated, the register s will be overflowed. the overflow is indicated by the cntov_is bit (b0, ints2,...) and will induce an inter- rupt reported by int if not masked by the cntov_im (b0, intm2,...). the process of manual error counter updating is illustrated in figure-29. figure-29 manual error counter updating read the errch & errcl registers in the next second tmov_is is cleared after a '1' is written to it data in the error counter transfers to the errch & errcl registers the error counter is cleared one second expired? (tmov_is = 1 ?) counting automatic error counter updating (cnt_md = 1) no yes repeat the same process in the next second read the errch & errcl registers in the next round data in the error counter transfers to the errch & errcl registers the error counter is cleared a transition from '0' to '1' on cnt_stop ? counting manual error counter updating (cnt_md = 0) no yes repeat the same process in the next round (cnt_stop must be cleared before the next round)
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 51 december 7, 2005 3.4.7 receive /transmit multiplex function (rmf / tmf) indication 3.4.7.1 rmfn indication in receive single rail nrz form at mode, the rdnn/rmfn pin is used as rmfn. in receive dual rail sliced mode, the rclkn/rmfn pin is used as rmfn. refer to table-2 multiplex pin used in receive system interface for details. rmfn can indicate the status of prbs/arb, lais, lexz, lbpv, lexz + lbpv, llos, output recovered clock (rclk) or xor output of positive and negative sliced data, as selected by the rmf_def[2:0] bits (b7~5, rcf1,...). refer to table-13 for details. table-13 rmfn indication rmf_def[2:0] indication on rmf details 000 prbs/arb rmfn is high if prbs/arb is detected in synchronizati on in the receive path. during the synchronization, rmfn goes low for a e1 clock cycle if a prbs/arb error is detected. rmfn is low if prbs/arb is out of synchronization. refer to section 3.4.5 prbs, qrss, arb and ib pattern generation and detection. 001 line alarm indication signal (lais) rmfn is high if ais is detected in the receive path and low if it is cleared. this indication corresponds to the lais_s bit (b6, stat1,...). refer to section 3.4.4 alarm indication signal (ais) detection and generation. 010 xor result of positive and negative sliced data rmfn outputs xor data of positive and negative sliced data. 011 recovered clock (rclk) rmfn outputs the recovered clock as rclkn. all the description about rclkn is applicable for rmfn. 100 line excessive zeroes (lexz) rmfn goes high for a e1 clock cycle if an exz is detected in the receive path, otherwise it is low. refer to section 3.4.2 excessive zeroes (exz) detection. 101 line bipolar violation (lbpv) rmfn goes high for a e1 clock cycle if a bpv/cv is detected in th e receive path, otherwis e it is low. refer to section 3.4.1 bipolar violation (bpv) / code violation (cv) detect ion and bpv insertion. 110 lexz + lbpv rmfn goes high for a e1 clock cycle if an exz or a bpv/cv is detected in the rece ive path, otherw ise it is low. 111 line loss of signal (llos) rmfn is high if los is detected in the receive path and low if it is cleared. this indication corresponds to the llos_s bit (b0, stat0,...). refer to section 3.4.3.1 line los (llos).
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 52 december 7, 2005 3.4.7.2 tmfn indication in transmit single rail nrz format mode and transmit dual rail rz format mode, the tdnn/tmfn pin is used as tmfn. refer to table-3 multiplex pin used in transmit system interface for details. tmfn can indicate the status of prbs/arb, sais, toc, tlos, sexz, sbpv, sexz + sbpv or slos, as selected by the tmf_def[2:0] bits (b7~5, tcf1,...). however, the indication of sbpv, sexz + sbpv and slos is disabled aut omatically in transmit single rail nrz format mode. refer to table-14 for details. table-14 tmfn indication tmf_def[2:0] indication on tmf details 000 prbs/arb tmfn is high if prbs/arb is detected in synchroni zation in the transmit path. during the synchronization, tmfn goes low for a e1 clock cycle if a pr bs/arb error is detected. tmfn is low if prbs/arb is out of synchronization. 001 system alarm indication signal (sais) tmfn is high if ais is detected in the transmit path and low if it is cleared. this indication corresponds to the sais_s bit (b7, stat1,...). refer to section 3.4.4 alarm indication signal (ais) detection and generation. 010 transmit over current (toc) tmfn is high if transmit over current is detected and low if it is cleared. this indication corresponds to the toc_s bit (b4, stat0,...). refer to section 3.2.5.1 transmit over current protection. 011 transmit loss of signal (tlos) tmfn is high if los is detected in the transmit line side and low if it is cleared. this indication corresponds to the tlos_s bit (b2, stat0,...). refer to section 3.4.3.3 transmit los (tlos). 100 system excessive zeroes (sexz) tmfn goes high for a e1 clock cycle if an exz is detected in the transmit path, otherwise it is low. refer to section 3.4.2 excessive zeroes (exz) detection 101 system bipolar violation (sbpv) * tmfn goes high for a e1 clock cycle if a bpv/cv is detected in the transmit path, otherwise it is low. refer to section 3.4.1 bipolar violation (bpv) / code violation (cv) detection and bpv insertion. 110 system excessive zeroes (sexz) + system bipolar violation (sbpv) * tmfn goes high for a e1 clock cycle if an exz or a bpv/cv is detected in t he transmit path, otherwise it is low. 111 system loss of signal (slos) * tmfn is high if los is detected in the transmit system side and low if it is cleared. this indication corresponds to the slos_s bit (b1, stat0,...). refer to section 3.4.3.2 system los (slos). note: * in transmit single rail nrz format mode, the corresponding indi cation is disabled and the co rresponding setting is reserved.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 53 december 7, 2005 3.4.8 loopback there are four kinds of loopback: ? analog loopback ? remote loopback ? digital loopback ? dual loopback refer to figure-1 for loopback location. 3.4.8.1 analog loopback analog loopback is enabled by the alp bit (b0, loop,...). the data stream to be transmitted on the ttipn/ tringn pins is internally looped to the rtipn/rringn pins. in analog loopback mode, the data stream to be transmitted is still output to the line side, while the data stream received from the line side is covered by the analog loopback data. anytime when analog loopback is set, the other loopbacks (i.e., digital loopback and remote loopback) are disabled. in analog loopback, the priority of the diagnostic facilities in the receive path is: pattern generation > looped data. ais generation is disabled in both the receive path and the transmit path. refer to figure- 30. figure-30 priority of diagnostic facilities during analog loopback tx path bpv/cv, exz, slos, ais, pattern detection pattern generation ais generation x rx path llos detection ais generation x bpv/cv, exz, ais, pattern detection pattern generation analog loopback
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 54 december 7, 2005 3.4.8.2 remote loopback remote loopback can be configured manually or automatically. either manual remote loopback configuration or automatic remote loopback configuration will enable remote loopback. manual remote loopback is enabled by the rlp bit (b1, loop,...). automatic remote loopback is enabled when the pattern detection is assigned in the receive path (i.e., the pd_pos bit (b3, pd,...) is ?0?) and the autolp bit (b3, loop,...) is ?1?. the corresponding channel will enter remote loopback when the activate ib code is detected in the receive path for more than 5.1 sec.; and will return from remote loop- back when the deactivate ib code is detected in the receive path for more than 5.1 sec. refer to section inband loopback (ib) detection on page 49 for details. when automatic remote loopback is active, setting the autolp bit (b3, loop,...) back to ?0? will also stop automatic remote loopback. the setting of the pd_pos bit (b3, pd,...) should not be changed during automatic remote loopback. the autolp_s bit (b7, stat0,...) indicates the automatic remote loopback status. in remote loopback mode, the data stream output from the rja (if enabled) is internally looped to the waveform shaper. the data stream received from the line side is still out put to the system side, while the data stream input from the system side is covered by the remote loop- back data and the status on tclkn does not affect the remote loop- back. however, the bpv/cv, exz, slos, ais and pattern detection in the transmit path still monitors the data stream input from the system side. in remote loopback mode, the priori ty of the diagnostic facilities in the receive path is: pattern generation > ais generation; the priority of the diagnostic facilities in the transmit path is: pattern generation > looped data. ais generation is disabled in the transmit path. refer to figure-31. figure-31 priority of diagnostic facilities during ma nual remote loopback tx path bpv/cv, exz, slos, ais, pattern detection pattern generation ais generation x rx path llos, ais detection ais generation bpv/cv, exz, pattern detection pattern generation remote loopback
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 55 december 7, 2005 3.4.8.3 digital loopback the digital loopback can be configured manually or automatically. either manual digital loopback configur ation or automatic digital loop- back configuration will enable digital loopback. manual digital loopback is enabled by the dlp bit (b2, loop,...). automatic digital loopback is enabled when the pattern detection is assigned in the transmit path (i.e., the pd_pos bit (b3, pd,...) is ?1?) and the autolp bit (b3, loop,...) is ?1?. the corresponding channel will enter digital loopback when the activa te ib code is detected in the transmit path for more than 5.1 sec.; and will return from digital loop- back when the deactivate ib code is detected in the transmit path for more than 5.1 sec. refer to section inband loopback (ib) detection on page 49 for details. when automatic digital loopback is active, setting the autolp bit (b3, loop,...) back to ?0? will also stop automatic digital loopback. the setting of the pd_pos bit (b3, pd,...) should not be changed during automatic digital loopback. the autolp_s bit (b7, stat0,...) indicates the automatic digital loopback status. in digital loopback mode, the data stream output from the tja (if enabled) is internally looped to the decoder (if enabled). the data stream to be transmitted is still output to the line side, while the data stream received from the line side is covered by the digital loopback data. however, llos and ais detection in the receive path still monitors the data stream received from the line side. in digital loopback mode, the priority of the diagnostic facilities in the receive path is: pattern generation > looped data; the priority of the diag- nostic facilities in the transmit pat h is: pattern generation > looped data > ais generation. ais generation is disabled in the receive path. figure-32 priority of diagnostic facilities during digital loopback tx path bpv/cv, exz, slos, ais, pattern detection pattern generation ais generation rx path llos, ais detection ais generation x bpv/cv, exz, ais, pattern detection pattern generation digital loopback
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 56 december 7, 2005 3.4.8.4 dual loopback dual loopback refers to the simu ltaneous implementation of remote loopback and digital loopback. two kinds of combinations are supported: ? manual remote loopback + manual digital loopback; ? manual remote loopback + automatic digital loopback. note that when digital loopback is active, automatic remote loop- back is unavailable as the pattern det ection is within the digital loop. in dual loopback mode, the data stream received from the line side outputs from the rja (if enabled), loops to the waveform shaper inter- nally and does not output to the system side. the data stream to be transmitted from the system side outputs from the tja (if enabled), loops to the decoder (if enabled) internally and does not output to the line side. llos, ais detection in t he receive path monitors the data stream received from the line side. the bpv/cv, exz and pattern detec- tion in the receive path monitors the digital looped data. the bpv/cv, exz, slos, ais and pattern detection in the transmit path monitors the data stream input from the system side. manual remote loopback + manual digital loopback this combination of dual loopback is enabled when both manual remote loopback and manual digital loopback are enabled. manual remote loopback is enabled by the rlp bit (b1, loop,...). manual digital loopback is enabled by the dlp bit (b2, loop,...). in this condition, the priority of the diagnostic facilities in the receive path is: pattern generation > digital looped data; the priority of the diag- nostic facilities in the transmit path is: remote looped data > pattern generation. ais generation is disabled in both the receive path and the transmit path. refer to figure-33. manual remote loopback + automatic digital loopback this combination of dual loopback is enabled when both manual remote loopback and automatic digital loopback are enabled. manual remote loopback is enabled by the rl p bit (b1, loop,...). automatic digital loopback is enabled when the pattern detection is assigned in the transmit path (i.e., the pd_pos bit (b3, pd,...) is ?1?) and the autolp bit (b3, loop,...) is ?1?. the corresponding channel will enter digital loopback when the activate ib code is detected in the transmit path for more than 5.1 sec.; and will return from digital loopback when the deactivate ib code is detected in the transmit path for more than 5.1 sec. refer to section inband loopback (ib) detection on page 49 for details. when automatic digital loopback is active, setting the autolp bit (b3, loop,...) back to ?0? will also stop automatic digital loopback. the setting of the pd_pos bit (b3, pd,...) should not be changed during automatic digital loopback. the autolp _s bit (b7, stat0,...) indicates the automatic digital loopback status. in this condition, the priority of the diagnostic facilities in the receive path is: pattern generation > digital looped data. ais generation in both the receive path and the transmit path, the pattern generation in the transmit path are disabled. refer to figure-34.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 57 december 7, 2005 figure-33 priority of diagnostic facilities during manual remote loopback + manual digital loopback figure-34 priority of diagnostic facilities duri ng manual remote loopback + automatic digital loopback tx path bpv/cv, exz, slos, ais, pattern detection pattern generation ais generation x rx path llos, ais detection ais generation bpv/cv, exz, pattern detection pattern generation remote loopback x digital loopback tx path bpv/cv, exz, slos, ais, pattern detection pattern generation ais generation x rx path llos, ais detection ais generation bpv/cv, exz, pattern detection pattern generation remote loopback x digital loopback x
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 58 december 7, 2005 3.4.9 channel 0 monitoring channel 0 is a special channel. it can be used in normal operation as the other 21 channels, or it c an be used as a monitoring channel. channel 0 supports g.772 moni toring and jitter measurement. 3.4.9.1 g.772 monitoring selected by the mon[5:0] bits (b5~ 0, mon), any receiver or trans- mitter of the other 21 channels c an be monitored by channel 0 (as shown in figure-35). when the g.772 monitoring is implemented (the mon[5:0] bits (b5~0, mon) is not ?0?), the register s of the receiver of channel 0 should be the same as those of the selected receiver /transmitter except the line interface related registers. once the g.772 monitoring is implemented, the receiver of channel 0 switches to external impedance matching mode automatically, and the setting in the r_term[2:0] bits (b 2~0, rcf0,...) of channel 0 is ignored. during the g.772 monitoring, channel 0 processes as normal after data is received from the selected path and the operation of the moni- tored path is not effected. the signal which is monitored goes through the clock & data recovery of monitoring channel (cha nnel 0). the monitored clock can output on rclk0. the monitored data can be observed digitally on the output pin of rclk0, rd0/rdp0 and rdn0. los detector is still in use in channel 0 for the monitored signal. in monitoring mode, channel 0 can be configured to remote loop- back. the signal which is being monitored will output on ttip0 and tring0. the output signal can then be connected to a standard test equipment for non-intrusive monitoring. figure-35 g.772 monitoring rdn0/rmf0 rclk0/rmf0 rtip0 rring0 tclk0/tdn0 tdn0/tmf0 td0/tdp0 rdn/rdpn rdnn/rmfn rclkn/rmfn rtipn rringn tclkn/tdnn tdnn/tmfn tdn/tdpn ch 0 g.772 monitoring ttipn tringn ttip0 tring0 rd0/rdp0 any of the remaining channels
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 59 december 7, 2005 3.4.9.2 jitter measurement (jm) the rja of channel 0 consists of a jitter measurement (jm) module. when the rja is enabled in channel 0, the jm is used to measure the positive and negative peak value of the demodulated jitter signal of the received data stream. the bandwidth of the measured jitter is selected by the jm_bw bit (b0, jm). the greatest positive peak value monito red in a certain period is indi- cated by the jit_ph and jit_pl regi sters, while the greatest negative peak value monitored in the same per iod is indicated by the jit_nh and jit_nl registers. the relationshi p between the greatest positive /nega- tive peak value and the indication in the corresponding registers is: positive peak = [jit_ph, jit_pl] / 16 (uipp); negative peak = [jit_nh, jit_nl] / 16 (uipp). the period is determined by the jm_md bit (b1, jm). when the jm_md bit (b1, jm) is ?1?, the period is one second auto- matically. the one-second timer uses mclk as clock reference. the expiration of each one second will set the tmov_is bit (b0, inttm) and induce an interrupt reported by int if not masked by the tmov_im bit (b0, gcf). the tmov_is bit (b0, inttm) is cleared after a ?1? is written to this bit. when each one second expires, internal buffers transfer the greatest positive/negative peak value accumulated in this one second to the jit_ph and jit_pl / jit_nh and jit_nl registers respectively and the internal buffers will be cleared to start a new round measurement. the registers should be read in the next second, otherwise they will be overwritten. refer to figure-36 for the process. when the jm_md bit (b1, jm) is ?0?, the period is controlled by the jm_stop bit (b2, jm) manually. when there is a transition from ?0? to ?1? on the jm_stop bit (b2, jm), the internal buffers transfer the greatest positive/negative peak value accumulated in this period to the jit_ph and jit_pl / jit_nh and jit_nl registers respectively and the internal buffers will be cleared to start a new round measurement. the registers should be read in the next round of jitter measurement, otherwise they will be overwritten. refer to figure-37 for the process. figure-36 automatic jm updating figure-37 manual jm updating read the jit_ph, jit_pl & jit_nh, jit_nl registers in the next second tmov_is is cleared after a '1' is written to it the greatest peak value in the internal buffers transfers to the jit_ph & jit_pl / jit_nh & jit_nl registers respectively the internal buffers are cleared one second expired? (tmov_is = 1 ?) peak jitter measurement automatic jm updating (jm_md = 1) no yes repeat the same process in the next second read the jit_ph, jit_pl & jit_nh, jit_nl registers in the next round the greatest peak value in the internal buffers transfers to the jit_ph & jit_pl / jit_nh & jit_nl registers respectively the internal buffers are cleared a transition from '0' to '1' on jm_stop ? peak jitter measurement manual jm updating (jm_md = 0) no yes repeat the same process in the next round (jm_stop must be cleared before the next round)
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 60 december 7, 2005 3.5 clock inputs and outputs the idt82p2521 provides two kinds of clock outputs: ? free running clock outputs on clke1 ? receiver clock outputs on refa and refb - selected from any of the 22 recovered line clocks - driven by mclk (free running) - driven by external clka/clkb input a frequency synthesizer is also av ailable to scale refa to 8 different frequencies. the following clock inputs are provided: ? mclk as programmable reference timing for the idt82p2521. ? clka and clkb as optional input clock source for refa and refb respectively 3.5.1 free running clock outputs on clke1 an internal clock generator uses mclk as reference to generate all the clocks required by internal circ uits and clke1 outputs. mclk is a stable jitter-free 1 clock input with 50 ppm accuracy. the clock frequency of mclk is 2.048 x n mhz (1 n 8, n is an integer number), as determined by mcksel[3:0]. refer to chapter 2 pin description for details. the outputs on clke1 is free running (locking to mclk). the output of clke1 is determined by the clke1_en bit (b3, clkg) and the clke1 bit (b2, clkg). refer to table-15. 1. jitter is no more than 0.001 ui. table-15 clock output on clke1 control bits clock output on clke1 clke1_en clke1 0 (don?t-care) high-z 1 08 khz 1 2.048 khz
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 61 december 7, 2005 3.5.2 clock outputs on refa/refb the outputs on refa and refb can be enabled or disabled, as determined by the refa_en bit (b6, refa) and the refb_en bit (b6, refb) respectively. when the output is disabled, refa/refb is in high-z state. when the output is enabled, the output of refa and refb varies in different operations. refer to below for detailed description. refer to figure-38 and figure-39 for an overview of refa and refb output options in normal operation. 3.5.2.1 refa/refb in clock recovery mode in this mode (default), the clock of refa and refb is derived from the recovered clock of one of the 22 channels as selected by the refa[4:0] bits (b4~0,refa) and refb[4:0] bits (b4~0,refb). deter- mined by the fs_bypas bit (b4, re fcf) a frequency synthesizer can be enabled for refa (refer to section 3.5.2.2 frequency synthesizer for refa clock output). if the frequenc y synthesizer is disabled, refa will output the recovered 2.048 mhz clock depending on the line mode of the selected channel. refb output the recovered 2.048 mhz clock depending on the line mode of the selected channel. the recovered line clock can be output to refa and refb before or after it passed the receive jitter attenuator (rja) selected by the ja_bypas bit (b6, refcf). 3.5.2.2 frequency synthesizer for refa clock output for refa a frequency synthesizer can be enabled or bypassed (default) as selected by fs_bypass bit (b4, refcf). the output frequency is selected by the freq[2 :0] bits (b2~0, refcf). frequen- cies supported are 8 khz, 64 khz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 19.44 mhz or 32.768 mhz. 3.5.2.3 free run mode fo r refa clock output refa can also be selected to provide a free running clock locked to mclk. to enable this mode the frequency synthesizer has to be enabled by setting the fs_bypas bit (b4, refcf) to ?0?, and the free bit (b3, refcf) has to be set to ?1?. refa will provide a frequency selected by the freq[2:0] 1 bits (b2~0, refcf) which is a free running clock locked to mclk. 3.5.2.4 refa/refb driven by external clka/clkb input in this mode, the clock of refa and refb is driven from an external clock input of clka and clkb respectively. clka and clkb are selected as an input source by setting refa[4:0] bits (b4~0, refa) and refb[4:0] bits (b4~0, refb) to any value from ?11101? to ? 11111?. clka and clkb are an external e1 (2.048 mhz) clock input. the cka_e1 bit (b5, refa) and ckb_e1 bit (b5, refb) should be set to match the input clock frequency. determined by the fs_bypass bit (b4, refcf), a frequency synthesizer can be enabled for refa (refer to section 3.5.2.2 frequency synthesizer for refa clock output). if the frequency synthesizer is disabled, refa and refb will output the 2.048 mhz clock. 3.5.2.5 refa and refb in loss of signal (los) or loss of clock condition if the recovered clock of one of the 22 channels is selected as the clock source for refa and refb (refer to section 3.5.2.1 refa/refb in clock recovery mode) and line los (llos) is detected in the corre- sponding channel, the state of output on refa and refb can be selected by the refh bit (b5, refcf). if refh is set to ?1?, refa and refb will output a high level in case of llos. if refh is set to ?0? and llos is detected, refa and refb clock outputs will be locked to mclk while the selected clock frequency will remain unchanged. llos condition is set when llos_s bit (b0, stat0) is ?1?. refer to section 3.4.3.1 line los (llos). refer to figure-40 for a detailed overview of refa output in case of llos. refb output option is only determined by the refh bit (b5, refcf) to be locked to mclk or set to high level output. if clka is selected as the cloc k source for refa (refer to section 3.5.2.4 refa/refb driven by external clka/clkb input) and there is no clock input on clka for more than 8 e1 clock cycles if e1 mode is selected (i.e. cka_e1 bit (b5, refa) is ?1?), the state of the refa output is determined by the fs_bypas bit (b4, refcf) and the free bit (b3, refcf). in case t he frequency synthesizer is disabled (i.e. fs_bypas bit (b4, refcf) is ?0?). refa will output a high level. if the frequency synthesizer is enabled and the free bit (b3, refcf) is set to ?0?, refa will output a hi gh level. if the frequency synthesizer is enabled and the free bit (b3, refcf) is set to ?1?, refa will be locked to mclk. refer to figure-41 for a detailed overview of refa output in case of loss of clka. if clkb is selected as the clock sour ce for refb (refer to section section 3.5.2.4 refa/refb driven by external clka/clkb input) and there is no clock input on clkb for more than 8 e1 clock cycles if e1 mode is selected (i.e. ckb_e1 bit (b5, refb) is ?1?), the output on refb is determined by the refh bit (b5, re fcf). if refh is set to ?1?, refb will output a high level. if refh is set to ?0?, the refb clock output will be locked to mclk. 1. ?000? and ?011? are reserved for freq[2:0] in this mode.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 62 december 7, 2005 figure-38 refa output options in normal operation recovered clock of one of the 22 channels ja_bypas = 1 ? no clock is derived from the output of rja clock is derived from the output of rx clock & data recovery yes clka input selected by refa[4:0] fs_bypas = 1 ? no pass through a frequency synthesizer free = 1 ? output on refa is free running (locked to mclk). the frequency is programmed in freq[2:0] *. output on refa is locked to the selected clock source. the frequency is programmed in freq[2:0]. output the selected clock on refa yes no yes note *: '000' and '011' are reserved for freq[2:0] when refa is free running.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 63 december 7, 2005 figure-39 refb output options in normal operation figure-40 refa output in llos condition (when rclkn is selected) recovered clock of one of the 22 channels ja_bypas = 1 ? no clock is derived from the output of rja clock is derived from the output of rx clock & data recovery yes clkb input selected by refb[4:0] output on refb in llos condition. fs_bypas = 1 ? no pass through a frequency synthesizer. free = 1 ? output on refa is free running (locked to mclk). the frequency is programmed in freq[2:0] *. output high level. no yes yes refh = 1 ? yes no output on refa is free running (locked to mclk). the frequency is 2.048 mhz. refh = 1 ? yes no note *: '000' and '011' are reserved for fr eq[2:0] when refa is free running.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 64 december 7, 2005 figure-41 refa output in no clka condition (when clka is selected) no clock input on clka. fs_bypas = 1 ? no pass through a frequency synthesizer. free = 1 ? output on refa is free running (locked to mclk). the frequency is programmed in freq[2:0] *. output high level. no yes yes note *: '000' and '011' are reserved for freq[2:0] when refa is free running.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 65 december 7, 2005 3.5.3 mclk, master clock input mclk provides a stable referenc e timing for the idt82p2521. mclk should be a jitter-free 1 clock with 50 ppm accuracy. the clock frequency of mclk is set by pins mcksel[3:0] and can be n x 2.048 mhz with 1 n 8 (n is an integer number). refer to mcksel[3:0] pin description for details. if there is a loss of mclk (duty cycle is less than 30% for 10 s), the device will enter power down. in th is case, both the receive and transmit circuits are turned off. the pins on the line interface will be in high-z state. the pins on receive system in terface will be in high-z state or in low level, as selected by the rhz bit (b6, rcf0,...). the input on the transmit system interface is ignored and the output on the transmit system interface will be in high-z state. refer to section 3.1.7 receiver power down and section 3.2.7 transmitter power down for details. if mclk recovers after loss of mclk the device will be reset auto- matically. 3.5.4 xclk, internal reference clock input xclk is derived from mclk. for the respective channel, it is 2.048 mhz. xclk is used as sele ctable reference clock for ? pattern /ais generation ? rclkn in llos ? loss of tclkn to determine transmit output high-z. 1. jitter is no more than 0.001 ui.
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 66 december 7, 2005 3.6 interrupt summary there are altogether 20 kinds of in terrupt sources as listed in table- 16. among them, no.1 to no.19 are per-channel interrupt sources, while no. 20 is a global interrupt source. for interrupt sources from no.1 to no.10, the occurrence of the event will cause the corresponding status bit to be set to ?1?. and selected by the interrupt trigger edges select bit, either a transition from ?0? to ?1? or any transition from ?0? to ?1? or from ?1 ? to ?0? of the status bit will cause the interrupt status bit to be set to ?1?, which indicates the occurrence of an interrupt event. for interrupt sources from no.11 to no.20, the occurrence of the event will cause the corresponding interrupt status bit to be set to ?1?. all the interrupt can be masked by the glb_im bit (b1, gcf) globally or by the corresponding interrupt ma sk bit individually. for all the inter- rupt sources, if not masked, the oc currence of the interrupt event will trigger an interrupt indicated by the int pin. for per-channel interrupt sources, if not masked, the occurrenc e of the interrupt event will also cause the corresponding int_chn bit (intch1~4) to be set ?1?. an interrupt event is cleared by wr iting ?1? to the corresponding inter- rupt status bit. the int_chn bit (int ch1~4) will not be cleared until all the interrupts in the correspondi ng channel are acknowledged. the int pin will be inactive until all the interrupts are acknowledged. refer to figure-42 for interrupt service flow. table-16 interrupt summary no. interrupt source status bit interrupt trigger edges select bit interrupt status bit interrupt mask bit 1 tclkn is missing. tcklos_s (b3, stat0,...) tcklos_ies (b3, intes,...) tcklos_is (b3, ints0,...) tcklos_im (b3, intm0,...) 2 llos is detected. llos_s (b0, stat0,...) los_ies (b1, intes,...) llos_is (b0, ints0,...) llos_im (b0, intm0,...) 3 slos is detected. slos_s (b1, stat0,...) los_ies (b1, intes,...) slos _is (b1, ints0,...) slos_im (b1, intm0,...) 4 tlos is detected. tlos_s (b2, stat0,...) tlos_ies (b2, in tes,...) tlos_is (b2, ints0,...) tlos_im (b2, intm0,...) 5 lais is detected. lais_s (b6, stat1,...) ais_ies (b6, intes,...) lais_is (b6, ints1,...) lais_im (b6, intm1,...) 6 sais is detected. sais_s (b7, stat1,...) ais_ies (b6, intes,...) sais_is (b7, ints1,...) sais_im (b7, intm1,...) 7 toc is detected. toc_s (b4, stat0,...) toc_ies (b4, intes,...) toc_is (b4, ints0,...) toc_im (b4, intm0,...) 8 the prbs/arb pattern is detected syn- chronized. pa_s (b5, stat1,...) pa_ies (b5, intes,...) pa_is (b5, ints1,...) pa_im (b5, intm1,...) 9 activate ib code is detected. iba_s (b1, stat1,...) ib_ies (b0, intes,...) iba_is (b1, ints1,...) iba_im (b1, intm1,...) 10 deactivate ib code is detected. ibd_s (b0, stat1,...) ib_ies (b0, intes,...) ibd_is (b0, ints1,...) ibd_im (b0, intm1,...) 11 the fifo of the rja is overflow or underflow. - - rja_is (b5, ints0,...) rja_im (b5, intm0,...) 12 the fifo of the tja is overflow or underflow. - - tja_is (b6, ints0,...) tja_im (b6, intm0,...) 13 waveform amplitude is overflow. - - dac_is (b7, ints0,...) dac_im (b7, intm0,...) 14 sbpv is detected. - - sbpv_is (b5, ints2,...) sbpv_im (b5, intm2,...) 15 lbpv is detected. - - lbpv_is (b4, ints2,...) lbpv_im (b4, intm2,...) 16 sexz is detected. - - sexz_is (b3, ints2,...) sexz_im (b3, intm2,...) 17 lexz is detected. - - lexz_is (b2, ints2,...) lexz_im (b2, intm2,...) 18 prbs/arb error is detect ed. - - err_is (b1, ints2,...) err_im (b1, intm2,...) 19 the errch and errcl registers are overflowed. - - cntov_is (b0, ints2,...) cntov_im (b0, intm2,...) 20 one second time is over. - - tmov_ is (b0, inttm) tmov_im (b0, gcf)
idt82p2521 21(+1) channel high-density e1 line interface unit functional description 67 december 7, 2005 figure-42 interrupt service process int active read tmov_is read int_chn tmov_is = 1 ? yes serve the interrupt. write '1' to clear tmov_is. int_chn = 1 ? yes read the interrupt status bits in the corresponding channel. find the interrupt source and serve it. write '1' to clear the corresponding interrupt status bit. int_chn is cleared when all interrupts in the corresponding channel are cleared. no no
idt82p2521 21(+1) channel high-density e1 line interface unit miscellaneous 68 december 7, 2005 4 miscellaneous 4.1 reset the reset operation resets all register s, state machines as well as i/o pins to their default value or status. the idt82p2521 provides 4 kinds of reset: ? power-on reset; ? hardware reset; ? global software reset; ? per-channel software reset. the power-on, hardware and global software reset operations reset all the common blocks (including cl ock generator/synthesizer and micro- processor interface) and channel-rela ted parts. the per-channel soft- ware reset operation resets the channel-related parts. figure-43 shows a general overview of the reset options. during reset, all the line interf ace pins (i.e., ttipn/tringn and rtipn/rringn) are in high-z state. after reset, all the items listed in table-17 are true. figure-43 reset clock generator/ synthesizer microprocessor interface channel hardware reset global software reset power-on reset per-channel software reset table-17 after reset effect summary effect on ... power-on reset, hardware reset and global software reset per-channel software reset ttipn/tringn & rtipn/ rringn all ttipn/tringn & rtipn/rringn pins are in high-z state. only ttipn/tringn & rtipn/rr ingn in the corresponding chan- nel are in high-z. line interface mode not e1 mode. not e1 mode. system interface all channels are in dual rail nrz format. only the corresponding channel is in dual rail nrz format. general i/o pins (i.e., d[7:0] and gpio[1:0]) as input pins. (no effect) int open drain output. (no effect) clke1, refa, refb output enable. (no effect) llos, llos0 output enable. (no effect) tdo, sdo/ ack /rdy high-z. (no effect) state machines all state machines are reset. the state machines in the corresponding channel are reset. interrupt sources all interrupt sources are masked. the interrupt sources in the corresponding channel are masked. registers all registers are reset to their default value. the registers in the corresponding channel are reset to their default value except that there is no effect on the e1 bit.
idt82p2521 21(+1) channel high-density e1 line interface unit miscellaneous 69 december 7, 2005 4.1.1 power-on reset power-on reset is initiated duri ng power-up. when all vdd inputs (1.8v and 3.3v) reach approximately 60% of the standard value of vdd, power-on reset begins. if mclk is app lied, power-on reset will complete within 1 ms maximum; if mclk is not applied, the device remains in reset state. 4.1.2 hardware reset pulling the rst pin to low will initiate hardware reset. the reset cycle should be more than 1 s. if the rst pin is held low continuously, the device remains in reset state. 4.1.3 global software reset writing the rst register will initiate global software reset. once initi- ated, global software reset completes in 1 s maximum. 4.1.4 per-channel software reset writing a ?1? to the chrst bit (b1, chcf,...) will initiate per-channel software reset. once initiated, per-channel software reset completes in 1 s maximum and the chrst bit (b1, chcf,...) is self cleared. this reset is different from other resets, for: ? it does not reset the global registers, state machines and common pins (including the pins of cl ock generator, microprocessor inter- face and jtag interface); ? it does not reset the other channels. 4.2 microprocessor interface the microprocessor interface prov ides access to read and write the registers in the device. t he interface consists of: ? serial microprocessor interface; ? parallel motorola non-multip lexed microprocessor interface; ? parallel motorola multiplexed microprocessor interface; ? parallel intel non-multiplexed microprocessor interface; ? parallel intel multiplexed microprocessor interface. the microprocessor interface is selected by the p/ s , int/ mot and im pins, as shown in table-18. the in terfaced pins in different interfaces are also listed in table-18. refer to section 8.11 microprocessor inter- face timing for the timing characteristics. table-18 microprocessor interface p/ s int/ mot im microprocessor interface interfaced pins gndd open gndd serial microprocessor interface cs , sclk, sdi, sdo vddio gndd gndd parallel motorola non-multiplexed microprocessor interface cs , ds , r/ w , ack , d[7:0], a[10:0] open parallel motorola multiplexed microprocessor interface cs , as, ds , r/ w , ack , d[7:0], a[10:8] open gndd parallel intel non-multiplexed microprocessor interface cs , rd , wr , rdy, d[7:0], a[10:0] open parallel intel multiplexed microprocessor interface cs , ale, rd , wr , rdy, d[7:0], a[10:8]
idt82p2521 21(+1) channel high-density e1 line interface unit miscellaneous 70 december 7, 2005 4.3 power up no power up sequencing for the vdd inputs (1.8 v and 3.3 v) has to be provided for the idt82p2521. a power-on reset will be initiated during power up. refer to section 4.1 reset. 4.4 hitless protection switching (hps) sum- mary in today?s telecommunication syst ems, ensuring no traffic loss is becoming increasingly important. to combat these problems, redun- dancy protection must be built into the systems carrying this traffic. there are many types of redundancy protection schemes, including 1+1 and 1:1 hardware protection without the use of external relays. refer to figure-44, figure-45 and figure-46 fo r different protection schemes. the idt82p2521 provides an enhanced architecture to support both protection schemes. idt82p2521 highlights for hps support: ? independent programmable receive and transmit high impedance for tip and ring inputs and outputs to support 1+1 and 1:1 redun- dancy ? fully integrated receive termination, required to support 1:1 redun- dancy ? enhanced internal architecture to guarantee high impedance for tip and ring inputs and outputs during power off or power fail- ure ? asynchronous hardware control (o e, rim) for fast global high impedance of receiver and transmi tter (hot switching between working and backup board) figure-44 1+1 hps scheme, differential interface (shared common transformer) 1:2 tx liu on primary line card liu on backup line card backplane interface card 1:1 tx rx rx 120 ? oe rim oe rim hot switch control vddtn ? vddtn ? ? vddrn ? vddrn vddtn ? vddtn ? ? vddrn ? vddrn rx: partially internal impedance matching mode. a fixed external 120 ? resistor is placed on the backplane and provides a common termination for e1 applications. the r_term[2:0] bits (b2~0, rcf0,...) setting is as follows: ?010? for e1 120 ? twisted pair cable and ?011? for e1 75 ? coaxial cable. tx: internal impedance matching mode. the t_term[2:0] bits (b2~0, tc f0,...) setting is as follows: ?010? for e1 120 ? twisted pair cable and ?011? for e1 75 ? coaxial cable.
idt82p2521 21(+1) channel high-density e1 line interface unit miscellaneous 71 december 7, 2005 figure-45 1:1 hps scheme, differential interface (individual transformer) tx primary card backup card tx rx rx oe rim oe rim hot switch control 1:2 1:2 1:1 1:1 vddtn ? vddtn ? ? vddrn ? vddrn vddtn ? vddtn ? ? vddrn ? vddrn rx: fully internal impedance matching mode. in this mode, there is no external resistor required. the r_term[2:0] bits (b2~0, rcf0, ...) setting is as follows: ?010? for e1 120 ? twisted pair cable and ?011? for e1 75 ? coaxial cable. tx: internal impedance matching mode. the t_term[2:0] bits (b2~0, tcf0,...) setting is as follows: ?010? for e1 120 ? twisted pair cable and ?011? for e1 75 ? coaxial cable.
idt82p2521 21(+1) channel high-density e1 line interface unit miscellaneous 72 december 7, 2005 figure-46 1+1 hps scheme, e1 75 ohm single-ended interface (shared common transformer) rx: 75 ? external impedance matching mode. in this mode, there is no external resistor required. the rim pin should be left open and th e configuration of the r_term[2:0] bits (b2~0, rcf0,...) is ignored. tx: 75 ? internal impedance matching mode. the t_term[2:0] bits (b2~0, tcf0,...) should be set to ?011?. primary line card backup line card tx tx rx rx oe rim oe rim hot switch control 4.7 f 19 ? 0.47 f 1:2 1:2 vddtn ? ? vddrn
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 73 december 7, 2005 5 programming information 5.1 register map 5.1.1 global register address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page common control 000 id - device id register id7 id6 id5 id4 id3 id2 id1 id0 p 77 040 rst - global reset register rs t7 rst6 rst5 rst4 rst3 rst2 rst1 rst0 p 77 080 gcf - global configuration register - - - copy int_pin1 int_pin0 glb_im tmov_im p 78 0c0 mon - g.772 monitor configura- tion register - - mon5 mon4 mon3 mon2 mon1 mon0 p 79 100 gpio - general purpose i/o pin definition register - - - - level1 level0 dir1 dir0 p 80 reference clock timing option 1c0 clkg - clke1 generation con- trol register - - - - clke1_en clke1 - - p 80 200 refcf - refa/b output con- figuration register - ja_bypas refh fs_bypas free freq2 freq1 freq0 p 81 240 refa - refa clock sources configuration register - refa_en cka_e1 refa4 refa3 refa2 refa1 refa0 p 83 280 refb - refb clock sources configuration register - refb_en ckb_e1 refb4 refb3 refb2 refb1 refb0 p 83 interrupt indication 2c0 intch1 - interrupt requisition source register 1 int_ch8 int_ch7 int_ch6 int_ch5 int_ch4 int_ch3 int_ch2 int_ch1 p 84 300 intch2 - interrupt requisition source register 2 int_ch16 int_ch15 int_ch14 int_ch13 int _ch12 int_ch11 int_ch10 int_ch9 p 84 340 intch3 - interrupt requisition source register 3 - - - int_ch21 int_ch20 int_ch19 int_ch18 int_ch17 p 84 380 intch4 - interrupt requisition source register 4 int_ch0------ -p85 3c0 inttm - one second timer interrupt status register -------tmov_isp85
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 74 december 7, 2005 5.1.2 per-channel register except for registers 7e5~7e9, wh ich are channel 0 related registers, only the address of channel 1 is list ed in the ?address (hex)? column of the following table. for the addresses of the other channels, refer to the description of each register. address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page channel control 001 chcf - channel configuration register - - - - - - chrst - p 85 ja configuration 002 tja - transmit jitter attenuation configuration register - - - tja_limt tja_en tja_dp1 tja_dp0 tja_bw p 86 003 rja - receive jitter attenuation configuration register rja_limt rja_en rja_dp1 rja_dp0 rja_bw p 87 transmit path configuration 004 tcf0 - transmit configuration register 0 - oe t_off thz_oc t_sing t_term2 t_term1 t_term0 p 88 005 tcf1 - transmit configuration register 1 tmf_def2 tem_def1 tmf_def0 tck_ es td_inv t_code t_md1 t_md0 p 89 006 puls - transmit pulse configu- ration register - - - - puls3 puls2 puls1 puls0 p 90 007 scal - amplitude scaling con- trol register - - scal5 scal4 scal3 scal2 scal1 scal0 p 91 008 awg0 - arbitrary waveform generation control register 0 - done rw samp4 samp3 samp2 samp1 samp0 p 91 009 awg1 - arbitrary waveform generation control register 1 - wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0 p 92 receive path configuration 00a rcf0 - receive configuration register 0 rckh rhz r_off r120in r_sing r_term2 r_term1 r_term0 p 93 00b rcf1 - receive configuration register 1 rmf_def2 rmf_def1 rmf_def0 rck_ es rd_inv r_code r_md1 r_md0 p 94 00c rcf2 - receive configuration register 2 ------mg1mg0p95 diagnostics 00d los - los configuration regis- ter lac alos2 alos1 alos0 talos1 talos0 tdlos1 tdlos0 p 96 00e err - error detection & inser- tion control register exz_def bpv_ins err_ins cnt_sel2 cnt _sel1 cnt_sel0 cnt_md cnt_stop p 97 00f aisg - ais generation control register - - - - asais_sl os asais_llo s alais_slo s alais_llo s p98 010 pg - pattern generation control register - pg_ck pg_en1 pg_en0 pg_pos pag_inv prbg_sel 1 prbg_sel 0 p99
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 75 december 7, 2005 011 pd - pattern detection control register - - - - pd_pos pad_inv pad_sel1 pad_sel0 p 100 012 arbl - arbitrary pattern gener- ation / detection low-byte reg- ister arb7 arb6 arb5 arb4 arb3 arb2 arb1 arb0 p 101 013 arbm - arbitrary pattern gen- eration / detection middle-byte register arb15 arb14 arb13 arb12 arb11 arb10 arb9 arb8 p 101 014 arbh - arbitrary pattern gener- ation / detection high-byte reg- ister arb23 arb22 arb21 arb20 arb19 arb18 arb17 arb16 p 101 015 ibl - inband loopback control register - - ibgl1 ibgl0 ibal1 ibal0 ibdl1 ibdl0 p 102 016 ibg - inband loopback genera- tion code definition register ibg7 ibg6 ibg5 ibg4 ibg3 ibg2 ibg1 ibg0 p 102 017 ibda - inband loopback detec- tion target activate code defini- tion register iba7 iba6 iba5 iba4 iba3 iba2 iba1 iba0 p 103 018 ibdd - inband loopback detec- tion target deactivate code definition register ibd7 ibd6 ibd5 ibd4 ibd3 ibd2 ibd1 ibd0 p 103 019 loop - loopback control reg- ister - - - - autolp dlp rlp alp p 104 interrupt edge selection 01a intes - interrupt trigger edges select register - ais_ies pa_ies toc_ies tcklos_i es tlos_ies los_ies ib_ies p 105 interrupt mask 01b intm0 - interrupt mask register 0 dac_im tja_im rja_im toc_im tcklos_i m tlos_im slos_im llos_im p 106 01c intm1 - interrupt mask register 1 sais_im lais_im pa_im - - - iba_im ibd_im p 107 01d intm2 - interrupt mask register 2 - - sbpv_im lbpv_im sexz_im lexz_im err_im cntov_im p 108 status indication 01e stat0 - status register 0 autolp_s - - toc_s tcklos_s tlos_s slos_s llos_s p 109 01f stat1 - status register 1 sai s_s lais_s pa_s - - - iba_s ibd_s p 110 interrupt status indication 020 ints0 - interrupt status regis- ter 0 dac_is tja_is rja_is toc_is tcklos_i s tlos_is slos_is llos_is p 111 021 ints1 - interrupt status regis- ter 1 sais_is lais_is pa_is - - - iba_is ibd_is p 112 022 ints2 - interrupt status regis- ter 2 - - sbpv_is lbpv_is sexz_is lexz_is err_is cntov_is p 113 address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 76 december 7, 2005 counter 023 errcl - error counter low- byte register errc7 errc6 errc5 errc4 errc3 errc2 errc1 errc0 p 114 024 errch - error counter high- byte register errc15 errc14 errc13 errc12 errc11 errc10 errc9 errc8 p 114 jitter measurement (channel 0 only) 7e5 jm - jitter measurement config- uration for channel 0 register - - - - - jm_stop jm_md jm_bw p 115 7e6 jit_pl - positive peak jitter measurement low-byte regis- ter jit_p7 jit_p6 jit_p5 jit_p4 jit_p3 jit_p2 jit_p1 jit_p0 p 115 7e7 jit_ph - positive peak jitter measurement high-byte regis- ter - - - - jit_p11 jit_p10 jit_p9 jit_p8 p 115 7e8 jit_nl - negative peak jitter measurement low-byte regis- ter jit_n7 jit_n6 jit_n5 jit_n4 jit_n3 jit_n2 jit_n1 jit_n0 p 116 7e9 jit_nh - negative peak jitter measurement high-byte regis- ter - - - - jit_n11 jit_n10 jit_n9 jit_n8 p 116 address (hex) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reference page
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 77 december 7, 2005 5.2 register description 5.2.1 global register id - device id register rst - global reset register address: 000h type: read default value: 20h bit name description 7 - 0 id[7:0] the id[7:0] bits are pre-set. the id[7:4] bits represent the device id for the idt82p2521. the id[3:0] bits represe nt the current version number (?0000? is for the first version). address: 040h type: write default value: 00h bit name description 7 - 0 rst[7:0] writing this register will initiate global software reset. this reset completes in 1 s maximum. 76543210 id7 id6 id5 id4 id3 id2 id1 id0 76543210 rst7 rst6 rst5 rst4 rst3 rst2 rst1 rst0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 78 december 7, 2005 gcf - global configuration register address: 080h type: read / write default value: 03h bit name description 7 - 5 - reserved. 4 copy when the per-channel register of one channel is written, this bit determines whether the written value is copied to the sa me reg- ister of the other channels simultaneously. 0: disable. (default) 1: enable. 3 - 2 int_pin[1:0] these two bits control the output on the int pin. x0: open drain, active low. (default) 01: push-pull, active low. 11: push-pull, active high. 1 glb_im this bit is a global configuration interrupt mask bit. 0: the per-channel interrupt will be generated when the per-channel interrupt mask bit is ?0? and the corresponding interrupt s ta- tus bit is ?1?. 1: mask all the per-channel interrupts. none per-channel interrupts can be generated. (default) 0 tmov_im this bit controls whether the interrupt is generated when one second time is over. this one second timer is locked to m clk. 0: enable. 1: mask. (default) 76543210 - - - copy int_pin1 int_pin0 glb_im tmov_im
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 79 december 7, 2005 mon - g.772 monitor configuration register address: 0c0h type: read / write default value: 00h bit name description 7 - 6 - reserved. 5 - 0 mon[5:0] these bits determine whether the g.772 monitor is implemented. when the g.772 monitor is implemented, these bits s elect one transmitter or receiver to be monitored by channel 0. 000000: no transmitter or receiver is monitored. (default) 000001: the receiver of channel 1 is monitored. 000010: the receiver of channel 2 is monitored. ...... 010100: the receiver of channel 20 is monitored. 010101: the receiver of channel 21 is monitored. 010110 ~ 011111: reserved. 100000: no transmitter or receiver is monitored. 100001: the transmitter of channel 1 is monitored. 100010: the transmitter of channel 2 is monitored. ...... 110100: the transmitter of channel 20 is monitored. 110101: the transmitter of channel 21 is monitored. 110110 ~ 111111: reserved. 76543210 - - mon5 mon4 mon3 mon2 mon1 mon0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 80 december 7, 2005 gpio - general purpose i/o pin definition register clkg - clke1 generation control register address: 100h type: read / write default value: 0fh bit name description 7 - 4 - reserved. 3 level1 when the gpio1 pin is defined as out put, this bit determines the output leve l on gpio1 and can be read and written. 0: output low level. 1: output high level. (default) when the gpio1 pin is defined as input, this bit indicates the input level on gpio1 and can only be read. 0: input low level. 1: input high level. (default) 2 level0 when the gpio0 pin is defined as out put, this bit determines the output leve l on gpio0 and can be read and written. 0: output low level. 1: output high level. when the gpio0 pin is defined as input, this bit indicates the input level on gpio0 and can only be read. 0: input low level. 1: input high level. (default) 1 dir1 this bit determines whether the gpio1 pin is used as output or input. 0: output. 1: input. (default) 0 dir0 this bit determines whether the gpio0 pin is used as output or input. 0: output. 1: input. (default) address: 1c0h type: read / write default value: 0fh bit name description 7 - 4 - reserved. 3 clke1_en this bit controls whether the output on the clke1 pin is enabled. 0: the output is disabled. clke1 is in high-z state. 1: the output is enabled. the frequency of clke1 is determined by the clke1 bit (b2, clkg). (default) 2 clke1 this bit is valid only when the clke1_en bit (b3, clkg) is ?1?. this bit selects the clock frequency output on the clke1 pin. 0: 8 khz. 1: 2.048 mhz. (default) 1- reserved. 0- reserved. 76543 2 1 0 - - - - level1 level0 dir1 dir0 76543210 --------
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 81 december 7, 2005 refcf - refa/b output configuration register address: 200h type: read / write default value: 30h bit name description 7-reserved. 6 ja_bypas this bit is valid only when the clock source for refa or refb is the recovered clock of one of the 22 channels in the correspond- ing receiver. this bit determines whether the selected recovered clock passes through the rja. 0: the selected recovered clock is derived from the output of rja. (default) 1: the selected recovered clock does not pass through the rja and is derived from the output of rx clock & data recovery. 5 refh this bit is valid only when the selected clock source is lost. this bit controls the output on refa/refb. for refa, this bit, together with the fs_bypas bit (b4, refcf) and the free bit (b3, refcf), controls the output on refa when the selected clock source is the recovered clock of one of the 22 channels; this bit is ignored when the selected clock source is clka. refer to the related table in the description of the free bit (b3, refcf). for refb: 0: output free running clock. the frequency is 2.048 mhz. 1: output high level. (default) 4 fs_bypas this bit determines whether the selected clock source for refa passes through an internal frequency synthesizer. 0: the internal frequency synthesizer is enabled. 1: the internal frequency synthesizer is bypassed. (default) 3 free this bit is valid only when the selected clock source for refa passes the internal frequency synthesizer in normal operation: 0: output the clock which is locked to the selected clock source and the frequency is programmed in the freq[2:0] bits (b2~0, refcf). (default) 1: output free running clock which is locked to mclk and the fr equency is programmed in the freq[2:0] bits (b2~0, refcf). when the selected clock source is lost, this bit, together with the fs_bypas bit (b4, refcf) and the refh bit (b5, refcf), controls the output on refa: 76543210 - ja_bypas refh fs_bypas free freq2 freq1 freq0 selected clock source fs_bypa s free refh output on refa clka 0 0 (don?t- care) high level. 1 free running clock, whose frequency is programmed in the freq[2:0] bits (b2~0, refcf). 1 (don?t-care) high level. recovered clock of one of the 22 chan- nels. 0 0 0 free running clock, whose frequency is programmed in the freq[2:0] bits (b2~0, refcf). 1 high level. 1 (don?t- care) free running clock, whose frequency is programmed in the freq[2:0] bits (b2~0, refcf). 1 (don?t- care) 0 free running clock, whose frequency is 2.048 mhz. 1 high level.
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 82 december 7, 2005 2 - 0 freq[2:0] these bits are valid only when the frequency synthesizer on refa is enabled. these bits determine the output cloc k frequency. freq[2:0] output when fs_bypas=0, free=0 and the frequency synthesizer uses rclkn or clka as reference clock output when fs_bypas=0 and free=1 (the frequency synthesizer is free running) 0 0 0 2.048 mhz - 0 0 1 8 khz 8 khz 0 1 0 64 khz 64 khz 0 1 1 reserved - 1 0 0 4.096 mhz 4.096 mhz 1 0 1 8.192 mhz 8.192 mhz 1 1 0 19.44 mhz 19.44 mhz 1 1 1 32.768 mhz 32.768 mhz
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 83 december 7, 2005 refa - refa clock sources configuration register refb - refb clock sour ces configuration register address: 240h type: read / write default value: 41h bit name description 7-reserved. 6 refa_en this bit controls whether the output on the refa pin is enabled. 0: the output is disabled. refa is in high-z state. 1: the output is enabled. (default) 5 cka_e1 this bit defines the input clock frequency on the clka pin. 0: reserved. (default) 1: input e1 clock. 4 - 0 refa[4:0] these bits select the clock source for refa. 00000: recovered clock of channel 0. 00001: recovered clock of channel 1. (default) 00010: recovered clock of channel 2. ...... 10100: recovered clock of channel 20. 10101: recovered clock of channel 21. 10110 ~ 11111: the input on clka. address: 280h type: read / write default value: 41h bit name description 7-reserved. 6 refb_en this bit controls whether the output on the refb pin is enabled. 0: the output is disabled. refb is in high-z state. 1: the output is enabled. (default) 5 ckb_e1 this bit defines the input clock frequency on the clkb pin. 0: reserved. (default) 1: input e1 clock. 4 - 0 refb[4:0] these bits select the clock source for refb. 00000: recovered clock of channel 0. 00001: recovered clock of channel 1. (default) 00010: recovered clock of channel 2. ...... 10100: recovered clock of channel 20. 10101: recovered clock of channel 21. 10110 ~ 11111: the input on clkb. 76543210 - refa_en cka_e1 refa4 refa3 refa2 refa1 refa0 76543210 - refb_en ckb_e1 refb4 refb3 refb2 refb1 refb0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 84 december 7, 2005 intch1 - interrupt requisition source register 1 intch2 - interrupt requisition source register 2 intch3 - interrupt requisition source register 3 address: 2c0h type: read / write default value: 00h bit name description 7 - 0 int_ch[8:1] these bits indicate whether there is an interr upt generated in the corresponding channel. the int_ch[8:1] bits correspond to channel 8 to 1 respectively. 0: no interrupt is generated or all the interrupts are cleared in the corresponding channel. (default) 1: at least one interrupt is generated in the corresponding channel. address: 300h type: read / write default value: 00h bit name description 7 - 0 int_ch[16:9] these bits indicate whether there is an interrupt generated in the corresponding channel. the int_ch[16:9] bit s correspond to channel 16 to 9 respectively. 0: no interrupt is generated or all the interrupts are cleared in the corresponding channel. (default) 1: at least one interrupt is generated in the corresponding channel. address: 340h type: read / write default value: 00h bit name description 7 - 5 - reserved. 4 - 0 int_ch[21:17] these bits indicate whether there is an interrupt generated in the corresponding channel. the int_ch[21:17] b its correspond to channel 21 to 17 respectively. 0: no interrupt is generated or all the interrupts are cleared in the corresponding channel. (default) 1: at least one interrupt is generated in the corresponding channel. 76543210 int_ch8 int_ch7 int_ch6 int_ch5 int_ch4 int_ch3 int_ch2 int_ch1 76543210 int_ch16 int_ch15 int_ch14 int_ch13 int_ch12 int_ch11 int_ch10 int_ch9 76543210 - - - int_ch21 int_ch20 int _ch19 int_ch18 int_ch17
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 85 december 7, 2005 intch4 - interrupt requisition source register 4 inttm - one second timer interrupt status register 5.2.2 per-channel register chcf - channel configuration register address: 380h type: read / write default value: 00h bit name description 7 int_ch0 this bit indicates whether there is an interrupt generated in channel 0. 0: no interrupt is generated or all the interrupts are cleared in channel 0. (default) 1: at least one interrupt is generated in channel 0. 6 - 0 - reserved. address: 3c0h type: read / write default value: 00h bit name description 7 - 1 - reserved. 0 tmov_is this bit is valid only when the tmov_im bit (b0, gcf) is ?0?. this bit indicates the interrupt status of one second tim e over. 0: no one second time over interrupt is generated; or a ?1? is written to this bit. (default) 1: one second time over interrupt is generated and is reported by the int pin. 76543210 int_ch0------- 76543210 -------tmov_is address: 001h, 041h, 081h, 0c 1h, 101h, 141h, 181h, 1c1h, (ch1~ch8) 201h, 241h, 281h, 2c1h, 301h, 341h, 381h, 3c1h, (ch9~ch16) 401h, 441h, 481h, 4c1h, 501h, (ch17~ch21) 7c1h (ch0) type: read / write default value: 00h bit name description 7 - 2 - reserved. 1 chrst writing a ?1? to this bit will initiate per-channel software reset. once initiated, per-channel software reset completes in 1 s maxi- mum. this bit is self cleared. 0-reserved. 76543 2 1 0 ----- -chrst-
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 86 december 7, 2005 tja - transmit jitter attenu ation configuration register address: 002h, 042h, 082h, 0c 2h, 102h, 142h, 182h, 1c2h, (ch1~ch8) 202h, 242h, 282h, 2c2h, 302h, 342h, 382h, 3c2h, (ch9~ch16) 402h, 442h, 482h, 4c2h, 502h, (ch17~ch21) 7c2h (ch0) type: read / write default value: 00h bit name description 7 - 5 - reserved. 4 tja_limt this bit determines whether the ja-limit function is enabled in the tja. 0: disable. (default) 1: enable. the speed of the tja outgoing data will be adjusted automatically if the fifo in the tja is 2-bit close to its full or emp- tiness. 3 tja_en this bit controls whether the tja is enabled to use. 0: disable. (default) 1: enable. 2 - 1 tja_dp[1:0] these bits select the depth of the tja fifo. 00: 128-bit. (default) 01: 64-bit. 1x: 32-bit. 0 tja_bw this bit selects the corner frequency for the tja. 0: 6.77 hz. (default) 1: 0.87 hz. 76543210 - - - tja_limt tja_en tja_dp1 tja_dp0 tja_bw
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 87 december 7, 2005 rja - receive jitter attenuat ion configuration register address: 003h, 043h, 083h, 0c 3h, 103h, 143h, 183h, 1c3h, (ch1~ch8) 203h, 243h, 283h, 2c3h, 303h, 343h, 383h, 3c3h, (ch9~ch16) 403h, 443h, 483h, 4c3h, 503h, (ch17~ch21) 7c3h (ch0) type: read / write default value: 00h bit name description 7 - 5 - reserved. 4 rja_limt this bit determines whether the ja-limit function is enabled in the rja. 0: disable. (default) 1: enable. the speed of the rja outgoing data will be adjusted automatically if the fifo in the rja is 2-bit close to its full or emptiness. 3 rja_en this bit controls whether the rja is enabled to use. 0: disable. (default) 1: enable. 2 - 1 rja_dp[1:0] these bits select the depth of the rja fifo. 00: 128-bit. (default) 01: 64-bit. 1x: 32-bit. 0 rja_bw this bit selects the corner frequency for the rja. 0: 6.77 hz. (default) 1: 0.87 hz. 76543210 - - - rja_limt rja_en rja_dp1 rja_dp0 rja_bw
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 88 december 7, 2005 tcf0 - transmit configuration register 0 address: 004h, 044h, 084h, 0c 4h, 104h, 144h, 184h, 1c4h, (ch1~ch8) 204h, 244h, 284h, 2c4h, 304h, 344h, 384h, 3c4h, (ch9~ch16) 404h, 444h, 484h, 4c4h, 504h, (ch17~ch21) 7c4h (ch0) type: read / write default value: 00h bit name description 7-reserved. 6 oe this bit determines the output of the line driver, i.e., the output on the ttipn and tringn pins. 0: high-z. (default) 1: normal operation. 5 t_off this bit determines whether the transmitter is powered down. 0: normal operation. (default) 1: power down. 4 thz_oc this bit determines the output of the line driver, i.e., the output on the ttipn and tringn pins when toc is detected. 0: the output current is limited to 100 map-p. (default) 1: the output current is limited to 100 map-p within the first 1 ms after the toc is detected and then the output is in high-z state when the toc is detected for more than 1 ms. 3 t_sing this bit determines the transmit line interface. 0: transmit differential line interface. both ttipn and tringn are used to transmit signal to the line side. (default) 1: transmit single ended line interface. only ttipn is used to transmit signal. tringn should be left open. 2 - 0 t_term[2:0] these bits select the impedance matching mode of the transmit path to match the cable impedance. 010: the 120 ? internal impedance matching is selected for e1 120 ? twisted pair cable (with transformer). 011: the 75 ? internal impedance matching is selected for e1 75 ? coaxial cable (with transformer). 110: the 120 ? internal impedance matching is selected for e1 120 ? twisted pair cable (transformer-less). 111: the external impedance matching is selected for e1 120 ? twisted pair cable or e1 75 ? coaxial cable (with transformer). others: reserved 76543210 - oe t_off thz_oc t_sing t_term2 t_term1 t_term0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 89 december 7, 2005 tcf1 - transmit configuration register 1 address: 005h, 045h, 085h, 0c 5h, 105h, 145h, 185h, 1c5h, (ch1~ch8) 205h, 245h, 285h, 2c5h, 305h, 345h, 385h, 3c5h, (ch9~ch16) 405h, 445h, 485h, 4c5h, 505h, (ch17~ch21) 7c5h (ch0) type: read / write default value: 01h bit name description 7 - 5 tmf_def[2:0] these bits are valid only in transmit dual rail rz format mode and transmit single rail nrz format mode. they determine the indication on the tmfn pin. 000: prbs/arb indication when the prbs/arb detection is switched to the transmit path. or reserved when the prbs/arb detection is switched to the receive path. (default) 001: sais indication. 010: toc indication. 011: tlos indication. 100: sexz indication. 101: sbpv indication in transmit dual rail rz format mode. reserved in transmit single ra il nrz format mode. 110: sexz + sbpv indication in transmit du al rail rz format mode. reserved in transmit single rail nrz format mode. 111: slos indication in transmit dual rail rz format mode. reserved in transmit single rail nrz format mode. 4 tck_es this bit selects the active edge of the tclkn pin. 0: falling edge. (default) 1: rising edge. 3 td_inv this bit determines the active level on the tdn, tdpn and tdnn pins. 0: active high. (default) 1: active low. 2 t_code this bit selects the line code rule for the transmit path. 0: hdb3. (default) 1: ami. 1 - 0 t_md[1:0] these bits determines the transmit system interface. 00: transmit single rail nrz format system interface. the data is input on tdn in nrz format and a 2.048 mhz clock is input on tclkn. 01: transmit dual rail nrz format system interface. the data is input on tdpn and tdnn in nrz format and a 2.048 mhz clock is input on tclkn. (default) 10: transmit dual rail rz format system interface. the data is input on tdpn and tdnn in rz format. 11: reserved. 76543210 tmf_def2 tmf_def1 tmf_def0 tck_es td_inv t_code t_md1 t_md0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 90 december 7, 2005 puls - transmit pulse configuration register address: 006h, 046h, 086h, 0c 6h, 106h, 146h, 186h, 1c6h, (ch1~ch8) 206h, 246h, 286h, 2c6h, 306h, 346h, 386h, 3c6h, (ch9~ch16) 406h, 446h, 486h, 4c6h, 506h, (ch17~ch21) 7c6h (ch0) type: read / write default value: 02h bit name description 7 - 4 - reserved. 3 - 0 puls[3:0] these bits select one of the eight preset waveform templates for short haul application or enable user-programmab le arbitrary waveform. 76543210 ----puls3puls2puls1puls0 puls[3:0] operation mode transmit clock cable impedance cab le range cable loss 0000 e1 2.048 mhz e1 75 ? differential interface, internal impedance matching mode - 0 ~ 12 db 0001 e1 2.048 mhz other e1 interfaces - 0 ~ 12 db 1xxx user-programmable arbitrary waveform others reserved.
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 91 december 7, 2005 scal - amplitude scaling control register awg0 - arbitrary waveform generation control register 0 address: 007h, 047h, 087h, 0c 7h, 107h, 147h, 187h, 1c7h, (ch1~ch8) 207h, 247h, 287h, 2c7h, 307h, 347h, 387h, 3c7h, (ch9~ch16) 407h, 447h, 487h, 4c7h, 507h, (ch17~ch21) 7c7h (ch0) type: read / write default value: 36h bit name description 7 - 6 - reserved. 5 - 0 scal[5:0] these bits specify a scaling factor to be applied to the amplitude of the waveform to be transmitted. the standard value is ?100001? for the waveform amplitude. if necessary, increasing or decreasing by ?1? from the standard valu e will result in 3% scaling up or down against the waveform amplitude. the scale range is from +100% to -100%. note: the default value for the scal[5:0] bits is ?110110?, which is different from the standard value ?100001?. address: 008h, 048h, 088h, 0c 8h, 108h, 148h, 188h, 1c8h, (ch1~ch8) 208h, 248h, 288h, 2c8h, 308h, 348h, 388h, 3c8h, (ch9~ch16) 408h, 448h, 488h, 4c8h, 508h, (ch17~ch21) 7c8h (ch0) type: read / write default value: 00h bit name description 7-reserved. 6 done this bit is valid only when the user-programmable arbitrary waveform is enabled (i.e., the puls[3:0] bits (b3~0, puls,...) are set to ?1xxx?). this bit determines whether to enable the data writin g/reading from ram. 0: disable. (default) 1: enable. 5 rw this bit is valid only when the user-programmable arbitrary waveform is enabled (i.e., the puls[3:0] bits (b3~0, puls,...) a re set to ?1xxx?). this bit deter mines read/write direction. 0: write data to ram. (default) 1: read data from ram. 4 - 0 samp[4:0] these bits are valid only when the user-programmable arbitrary waveform is enabled (i.e., the puls[3:0] bits (b3~ 0, puls,...) are set to ?1xxx?). these bits specify the ram sample address. 00000: the ram sample address is 0. (default) 00001: the ram sample address is 1. 00010: the ram sample address is 2. ...... 10001: the ram sample address is 17. 10010: the ram sample address is 18. 10011 ~ 11111: the ram sample address is 19. 76543210 - - scal5 scal4 scal3 scal2 scal1 scal0 76543210 - done rw samp4 samp3 samp2 samp1 samp0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 92 december 7, 2005 awg1 - arbitrary waveform generation control register 1 address: 009h, 049h, 089h, 0c 9h, 109h, 149h, 189h, 1c9h, (ch1~ch8) 209h, 249h, 289h, 2c9h, 309h, 349h, 389h, 3c9h, (ch9~ch16) 409h, 449h, 489h, 4c9h, 509h, (ch17~ch21) 7c9h (ch0) type: read / write default value: 00h bit name description 7-reserved. 6 - 0 wdat[6:0] these bits are valid only when the user-programmabl e arbitrary waveform is enabled (i.e., the puls[3:0] bits (b3~ 0, puls,...) are set to ?1xxx?). these bits contain the template sample data to be stored in ram which address is specified by the samp[4:0] bits (b4~0, awg0,...). they are not updated until new template sample data is written. 76543210 - wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 93 december 7, 2005 rcf0 - receive configuration register 0 address: 00ah, 04ah, 08ah, 0cah, 10ah, 14ah, 18ah, 1cah, (ch1~ch8) 20ah, 24ah, 28ah, 2cah, 30ah, 34ah, 38ah, 3cah, (ch9~ch16) 40ah, 44ah, 48ah, 4cah, 50ah, (ch17~ch21) 7cah (ch0) type: read / write default value: 47h bit name description 7 rckh this bit determines the output on rclkn when llos is detected. this bit is valid only when llos is detected and the ais an d pattern generation is disabled in the receive path. 0: xclk. (default) 1: high level. 6 rhz this bit determines the output of all receive system interfaced pins (including rdn, rdpn, rdnn, rmfn and rclkn) when the corresponding receiver is powered down. 0: low level. 1: high-z. (default) 5 r_off this bit determines whether the receiver is powered down. 0: normal operation. (default) 1: power down. 4 r120in this bit is valid only when the receive line interface is in receive differential mode and per-channel internal impedanc e matching configuration is enabled. this bit selects the internal impedance matching mode. 0: partially internal impedance matching mode. an internal programmable resistor (im) and a value-fixed external resistor (rr) are used. (default) 1: fully internal impedance matching mode. only an internal programmable resistor (im) is used. 3 r_sing this bit determines the receive line interface. 0: receive differential line interface. both rtipn and rringn are used to receive signal from the line side. (default) 1: receive single ended line interface. only rtipn is used to receive signal. rringn should be left open. 2 - 0 r_term[2:0] these bits are valid only when impedance matching is configured on a per-channel basis. these bits select the i mpedance matching mode of the receive path to match the cable impedance. in receive differential mode: 010: the 120 ? internal impedance matching is selected for e1 120 ? twisted pair cable. 011: the 75 ? internal impedance matching is selected for e1 75 ? coaxial cable. 1xx: external impedance matching is selected for e1 120 ? twisted pair cable and e1 75 ? coaxial cable. in receive single ended mode, only external impedance matching is supported and the setting of these bits is a don?t-care. (default) others: reserved. 76543210 rckh rhz r_off r120in r_sing r_term2 r_term1 r_term0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 94 december 7, 2005 rcf1 - receive configuration register 1 address: 00bh, 04bh, 08bh, 0cbh, 10bh, 14bh, 18bh, 1cbh, (ch1~ch8) 20bh, 24bh, 28bh, 2cbh, 30bh, 34bh, 38bh, 3cbh, (ch9~ch16) 40bh, 44bh, 48bh, 4cbh, 50bh, (ch17~ch21) 7cbh (ch0) type: read / write default value: 01h bit name description 7 - 5 rmf_def[2:0] these bits are valid only in receive single rail nrz format mode and receive dual rail sliced mode. they deter mine the out- put on the rmfn pin. 000: prbs/arb indication when the prbs/arb detection is swit ched to the receive path. or reserved when the prbs/arb detection is switched to the transmit path. (default) 001: lais indication. 010: xor data of positive and negative sliced data. 011: recovered clock (rclk). 100: lexz indication. 101: lbpv indication. 110: lexz + lbpv indication. 111: llos indication. 4 rck_es this bit selects the active edge of the rclkn pin. 0: rising edge. (default) 1: falling edge. 3 rd_inv this bit determines the active level on the rdn, rdpn and rdnn pins. 0: active high. (default) 1: active low. 2 r_code this bit selects the line code rule for the receive path. 0: hdb3. (default) 1: ami. 1 - 0 r_md[1:0] these bits determines the receive system interface. 00: receive single rail nrz format system interface. the data is output on rdn in nrz format and a 2.048 mhz recovered clock is output on rclkn. 01: receive dual rail nrz format system interface. the data is output on rdpn and rdnn in nrz format and a 2.048 mhz recovered clock is output on rclkn. (default) 10: receive dual rail rz format system interface. the data is output on rdpn and rdnn in rz format and a 2.048 mhz recov- ered clock is output on rclkn. 11: receive dual rail sliced system interface. the data is output on rdpn and rdnn in rz format directly after passing through the slicer. 76543210 rmf_def2 rmf_def1 rmf_def0 rc k_es rd_inv r_code r_md1 r_md0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 95 december 7, 2005 rcf2 - receive configuration register 2 address: 00ch, 04ch, 08ch, 0cch, 10ch, 14ch, 18ch, 1cch, (ch1~ch8) 20ch, 24ch, 28ch, 2cch, 30ch, 34ch, 38ch, 3cch, (ch9~ch16) 40ch, 44ch, 48ch, 4cch, 50ch, (ch17~ch21) 7cch (ch0) type: read / write default value: 00h bit name description 7 - 2 - reserved. 1 - 0 mg[1:0] these bits select the monitor gain. 00: 0 db. (default) 01: 20 db. 10: 26 db. 11: 32 db. 76543210 ------mg1mg0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 96 december 7, 2005 los - los configuration register address: 00dh, 04dh, 08dh, 0cdh, 10dh, 14dh, 18dh, 1cdh, (ch1~ch8) 20dh, 24dh, 28dh, 2cdh, 30dh, 34dh, 38dh, 3cdh, (ch9~ch16) 40dh, 44dh, 48dh, 4cdh, 50dh, (ch17~ch21) 7cdh (ch0) type: read / write default value: 15h bit name description 7 lac this bit selects the llos, slos and ais criteria. 0: g.775. (default) 1: etsi 300233 & i.431. 6 - 4 alos[2:0] these bits select the amplitude threshold (q). when the amplitude of the data is less than q vpp for n consecutiv e pulse inter- vals, llos is declared. the consecut ive pulse intervals (n) are determined by the lac bit (b7, los,...). the alos[2:0] settings for normal receive mode and line monitor mode are different. refer to below tables. 3 - 2 talos[1:0] these bits select the amplitude threshold. when the amplitude of the data is less than the threshold for a certa in period, tlos is declared. the period is determined by the tdlos bits (b1~0, los,...). when the amplitude of a pulse is above the threshold, tlos is cleared. for differential line interface: 00: 1.2 vp. 01: 0.9 vp. (default) 10: 0.6 vp. 11: 0.4 vp. for single ended line interface: 00: 0.61 vp. 01: 0.48 vp. (default) 10: 0.32 vp. 11: 0.24 vp. 76543210 lac alos2 alos1 alos0 talos1 talos0 tdlos1 tdlos0 alos[2:0] setting in normal receive mode alos[2:0] q (vpp) vs. 6.0 vpp (db) vs. 4.74 vpp (db) 000 0.5 21.58 19.54 001 (default) 0.7 18.66 16.61 010 0.9 16.48 14.43 011 1.2 13.98 11.93 100 1.4 12.64 10.59 101 1.6 11.48 9.43 110 1.8 10.46 8.41 111 2.0 9.54 7.49 alos[2:0] setting in line monitor mode alos[2:0] q (vpp) vs. 6.0 vpp (db) vs. 4.74 vpp (db) 000 1.0 15.56 13.52 001 (default) 1.4 12.64 10.59 010 1.8 10.46 8.41 011 2.2 8.71 6.67 1xx reserved.
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 97 december 7, 2005 err - error detection & in sertion control register 1 - 0 tdlos[1:0] these bits select the period. when the amplitude of the data is less than a certain voltage for the period, tlos is declared. the voltage is determined by the talos bits (b3~2, los,...). 00: 16-pulse. 01: 32-pulse. (default) 1x: 64-pulse. address: 00eh, 04eh, 08eh, 0ceh, 10eh, 14eh, 18eh, 1ceh, (ch1~ch8) 20eh, 24eh, 28eh, 2ceh, 30eh, 34eh, 38eh, 3ceh, (ch9~ch16) 40eh, 44eh, 48eh, 4ceh, 50eh, (ch17~ch21) 7ceh (ch0) type: read / write default value: 00h bit name description 7 exz_def this bit selects the exz definition standard. 0: ansi. (default) 1: fcc. 6 bpv_ins this bit controls whether to insert a bipolar violati on (bpv) to the transmit path. writing ?1? to this bit will insert a bpv on the next available mark in the data stream to be transmitted. this bit is cleared once t he bpv insertion is completed. 5 err_ins this bit controls whether to insert a single bit error to the generated prbs/arb pattern. a transition from ?0? to ?1? on this bit will insert a single bit error to the generated prbs/arb pattern. this bit is cleared once the single bit error insertion is completed. 4 - 2 cnt_sel[2:0] these bits select what kind of error to be counted by the internal error counter. 000: disable. (default) 001: lbpv. 010: lexz. 011: lbpv + lexz. 100: sbpv. 101: sexz. 110: sbpv + sexz. 111: prbs/arb error. 1 cnt_md this bit determines whether the errch & errcl registers are updated automatically or manually. 0: manually by setting the cnt_stop bit (b0, err,...). (default) 1: every-one second automatically. 0 cnt_stop this bit is valid only when the cnt_md bit (b1, err,...) is ?0?. a transition from ?0? to ?1? on this bit updates the errch & errcl registers. this bit must be cleared before the next round. 76543210 exz_def bpv_ins err_ins cnt_sel2 cnt _sel1 cnt_sel0 cnt_md cnt_stop
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 98 december 7, 2005 aisg - ais generation control register address: 00fh, 04fh, 08fh, 0cfh, 10fh, 14fh, 18fh, 1cfh, (ch1~ch8) 20fh, 24fh, 28fh, 2cfh, 30fh, 34fh, 38fh, 3cfh, (ch9~ch16) 40fh, 44fh, 48fh, 4cfh, 50fh, (ch17~ch21) 7cfh (ch0) type: read / write default value: 00h bit name description 7 - 4 - reserved. 3 asais_slos this bit controls t he ais generation in the receiv e path once slos is detected. 0: disable. (default) 1: enable. 2 asais_llos this bit controls the ais generati on in the receive path once llos is detected. 0: disable. (default) 1: enable. 1 alais_slos this bit controls the ais generation in the transmit path once slos is detected. 0: disable. (default) 1: enable. 0 alais_llos this bit controls the ais generation in the transmit path once llos is detected. 0: disable. (default) 1: enable. 76543210 ---- asais_slos asais_llos alais_slos alais_llos
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 99 december 7, 2005 pg - pattern generation control register address: 010h, 050h, 090h, 0d 0h, 110h, 150h, 190h, 1d0h, (ch1~ch8) 210h, 250h, 290h, 2d0h, 310h, 350h, 390h, 3d0h, (ch9~ch16) 410h, 450h, 490h, 4d0h, 510h, (ch17~ch21) 7d0h (ch0) type: read / write default value: 00h bit name description 7-reserved. 6 pg_ck this bit selects the reference clock when the pattern (including prbs, arb & ib) is generated. when the pattern is generated in the receive path: 0: xclk. (default) 1: recovered clock from the received signal. when the pattern is generated in the transmit path: 0: xclk. (default) 1: transmit clock, i.e., the clock input on tclkn (in transmit single rail nrz format mode and in transmit dual rail nrz for- mat mode) or the clock recovered from the data input on tdpn and tdnn (in transmit dual rail rz format mode) 5 - 4 pg_en[1:0] these bits select the pattern to be generated. 00: disable. (default) 01: prbs. 10: arb. 11: ib. 3 pg_pos this bit selects the pattern (including prbs, arb & ib) generation direction. 0: transmit path. (default) 1: receive path. 2 pag_inv this bit controls whether to invert the generated prbs/arb pattern. 0: normal. (default) 1: invert. 1 - 0 prbg_sel[1:0] these bits are valid only when the prbs pattern is generated. they select the prbs pattern. 00: 2 20 - 1 qrss. (default) 01: 2 15 - 1 prbs. 1x: 2 11 - 1 prbs. 76543210 - pg_ck pg_en1 pg_en0 pg_pos pag_inv prbg_sel1 prbg_sel0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 100 december 7, 2005 pd - pattern detection control register address: 011h, 051h, 091h, 0d 1h, 111h, 151h, 191h, 1d1h, (ch1~ch8) 211h, 251h, 291h, 2d1h, 311h, 351h, 391h, 3d1h, (ch9~ch16) 411h, 451h, 491h, 4d11h, 511h, (ch17~ch21) 7d1h (ch0) type: read / write default value: 03h bit name description 7 - 4 - reserved. 3 pd_pos this bit selects the pattern (including prbs, arb & ib) detection direction. 0: receive path. (default) 1: transmit path. 2 pad_inv this bit controls whether to invert the data before prbs/arb detection. 0: normal. (default) 1: invert. 1 - 0 pad_sel[1:0] these bits select the desired prbs/arb pattern to be detected. 00: 2 20 - 1 qrss. 01: 2 15 - 1 prbs. 10: 2 11 - 1 prbs. 11: arb. (default) 76543210 - - - - pd_pos pad_inv pad_sel1 pad_sel0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 101 december 7, 2005 arbl - arbitrary pattern generati on / detection low-byte register arbm - arbitrary pattern generation / detection middle-byte register arbh - arbitrary pattern generati on / detection high-byte register address: 012h, 052h, 092h, 0d 2h, 112h, 152h, 192h, 1d2h, (ch1~ch8) 212h, 252h, 292h, 2d2h, 312h, 352h, 392h, 3d2h, (ch9~ch16) 412h, 452h, 492h, 4d2h, 512h, (ch17~ch21) 7d2h (ch0) type: read / write default value: 55h bit name description 7 - 0 arb[7:0] these bits, together with the arb[23:8] bits, define the arb pattern to be generated or detected. the arb23 bit is the first bit to be generated or detected and the arb0 bit is the last bit to be generated or detected. address: 013h, 053h, 093h, 0d 3h, 113h, 153h, 193h, 1d3h, (ch1~ch8) 213h, 253h, 293h, 2d3h, 313h, 353h, 393h, 3d3h, (ch9~ch16) 413h, 453h, 493h, 4d3h, 513h, (ch17~ch21) 7d3h (ch0) type: read / write default value: 55h bit name description 7 - 0 arb[15:8] (refer to the description of the arbl register.) address: 014h, 054h, 094h, 0d 4h, 114h, 154h, 194h, 1d4h, (ch1~ch8) 214h, 254h, 294h, 2d4h, 314h, 354h, 394h, 3d4h, (ch9~ch16) 414h, 454h, 494h, 4d4h, 514h, (ch17~ch21) 7d4h (ch0) type: read / write default value: 55h bit name description 7 - 0 arb[23:16] (refer to the description of the arbl register.) 76543210 arb7 arb6 arb5 arb4 arb3 arb2 arb1 arb0 76543210 arb15 arb14 arb13 arb12 arb11 arb10 arb9 arb8 76543210 arb23 arb22 arb21 arb20 arb19 arb18 arb17 arb16
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 102 december 7, 2005 ibl - inband loopback control register ibg - inband loopback generation code definition register address: 015h, 055h, 095h, 0d 5h, 115h, 155h, 195h, 1d5h, (ch1~ch8) 215h, 255h, 295h, 2d5h, 315h, 355h, 395h, 3d5h, (ch9~ch16) 415h, 455h, 495h, 4d5h, 515h, (ch17~ch21) 7d5h (ch0) type: read / write default value: 01h bit name description 7 - 6 - reserved. 5 - 4 ibgl[1:0] these bits define the length of the valid ib ge neration code programmed in the ibg[7:0] bits (b7~0, ibg,...). 00: 5-bit long in the ibg[4:0] bits (b4~0, ibg,...). (default) 01: 6-bit long in the ibg[5:0] bits (b5~0, ibg,...). 10: 7-bit long in the ibg[6:0] bits (b6~0, ibg,...). 11: 8-bit long in the ibg[7:0] bits (b7~0, ibg,...). 3 - 2 ibal[1:0] these bits define the length of the valid target activate ib detection code programmed in the iba[7:0] bits (b7~0 , ibda,...). 00: 5-bit long in the iba[4:0] bits (b4~0, ibda,...). (default) 01: 6-bit long in the iba[5:0] bits (b5~0, ibda,...). 10: 7-bit long in the iba[6:0] bits (b6~0, ibda,...). 11: 8-bit long in the iba[7:0] bits (b7~0, ibda,...). 1 - 0 ibdl[1:0] these bits define the length of the valid target deactivate ib detection code programmed in the ibd[7:0] bits (b7 ~0, ibdd,...). 00: 5-bit long in the ibd[4:0] bits (b4~0, ibdd,...). 01: 6-bit long in the ibd[5:0] bits (b5~0, ibdd,...). (default) 10: 7-bit long in the ibd[6:0] bits (b6~0, ibdd,...). 11: 8-bit long in the ibd[7:0] bits (b7~0, ibdd,...). address: 016h, 056h, 096h, 0d 6h, 116h, 156h, 196h, 1d6h, (ch1~ch8) 216h, 256h, 296h, 2d6h, 316h, 356h, 396h, 3d6h, (ch9~ch16) 416h, 456h, 496h, 4d6h, 516h, (ch17~ch21) 7d6h (ch0) type: read / write default value: 01h bit name description 7 - 0 ibg[7:0] the ibg[x:0] bits define the content of the ib generation code. the ?x? is determined by the ibgl[1:0] bits (b5~4, ibl,...). the ibg0 bit is the last bit to be generated. the code is generated repeatedly until the ib generation is stopped. 76543210 - - ibgl1 ibgl0 ibal1 ibal0 ibdl1 ibdl0 76543210 ibg7 ibg6 ibg5 ibg4 ibg3 ibg2 ibg1 ibg0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 103 december 7, 2005 ibda - inband loopback detection targ et activate code definition register ibdd - inband loopback detection target deactivate code definition register address: 017h, 057h, 097h, 0d 7h, 117h, 157h, 197h, 1d7h, (ch1~ch8) 217h, 257h, 297h, 2d7h, 317h, 357h, 397h, 3d7h, (ch9~ch16) 417h, 457h, 497h, 4d7h, 517h, (ch17~ch21) 7d7h (ch0) type: read / write default value: 01h bit name description 7 - 0 iba[7:0] the iba[x:0] bits define the content of the target activate ib detection code. the ?x? is determined by the ibal[1 :0] bits (b3~2, ibl,...). the iba0 bit is the last bit to be detected. address: 018h, 058h, 098h, 0d 8h, 118h, 158h, 198h, 1d8h, (ch1~ch8) 218h, 258h, 298h, 2d8h, 318h, 358h, 398h, 3d8h, (ch9~ch16) 418h, 458h, 498h, 4d8h, 518h, (ch17~ch21) 7d8h (ch0) type: read / write default value: 09h bit name description 7 - 0 ibd[7:0] the ibd[x:0] bits define the content of the target deactivate ib detection code. the ?x? is determined by the ibdl [1:0] bits (b1~0, ibl,...). the ibd0 bit is the last bit to be detected. 76543210 iba7 iba6 iba5 iba4 iba3 iba2 iba1 iba0 76543210 ibd7 ibd6 ibd5 ibd4 ibd3 ibd2 ibd1 ibd0
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 104 december 7, 2005 loop - loopback control register address: 019h, 059h, 099h, 0d 9h, 119h, 159h, 199h, 1d9h, (ch1~ch8) 219h, 259h, 299h, 2d9h, 319h, 359h, 399h, 3d9h, (ch9~ch16) 419h, 459h, 499h, 4d9h, 519h, (ch17~ch21) 7d9h (ch0) type: read / write default value: 00h bit name description 7 - 4 - reserved. 3 autolp this bit determines whether automatic digital/remote loopback is enabled. 0: automatic digital/remote loopback is disabled. (default) 1: automatic digital/remote loopback is enabled. the corresponding channel will enter digital/remote loopback when the acti- vate ib code is detected in the transmit/receive path for more than 5.1 sec.; and will return from digital/remote loopback when the deactivate ib code is detected in the transmit/receive path for more than 5.1 sec. 2 dlp this bit controls whether digital loopback is enabled. 0: disable. (default) 1: enable. 1 rlp this bit controls whether remote loopback is enabled. 0: disable. (default) 1: enable. 0 alp this bit controls whether analog loopback is enabled. 0: disable. (default) 1: enable. 76543210 ----autolpdlprlpalp
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 105 december 7, 2005 intes - interrupt trigger edges select register address: 01ah, 05ah, 09ah, 0d ah, 11ah, 15ah, 19ah, 1dah, (ch1~ch8) 21ah, 25ah, 29ah, 2dah, 31ah, 35ah, 39ah, 3dah, (ch9~ch16) 41ah, 45ah, 49ah, 4dah, 51ah, (ch17~ch21) 7dah (ch0) type: read / write default value: 00h bit name description 7-reserved. 6 ais_ies this bit selects the transition edge of the lais_s bit (b6, stat1,...) and the sais_s bit (b7, stat1,...). 0: a transition from ?0? to ?1? on the lais_s bit (b6, stat1,...) / the sais_s bit (b7, stat1,...) will set the lais_is bit (b6 , ints1,...) / the sais_is bit (b7, ints1,...) to ?1? respectively. (default) 1: any transition from ?0? to ?1? or from ?1? to ?0? on the lais_s bit (b6, stat1,...) / the sais_s bit (b7, stat1,...) will se t the lais_is bit (b6, ints1,...) / the sais_is bit (b7, ints1,...) to ?1? respectively. 5 pa_ies this bit selects the transition edge of the pa_s bit (b5, stat1,...). 0: a transition from ?0? to ?1? on the pa_s bit (b5, stat1,...) will set the pa_is bit (b5, ints1,...) to ?1?. (default) 1: any transition from ?0? to ?1? or from ?1? to ?0? on the pa _s bit (b5, stat1,...) will set the pa_is bit (b5, ints1,...) to ?1?. 4 toc_ies this bit selects the transition edge of the toc_s bit (b4, stat0,...). 0: a transition from ?0? to ?1? on the toc_s bit (b4, stat0,... ) will set the toc_is bit (b4, ints0,...) to ?1?. (default) 1: any transition from ?0? to ?1? or from ?1? to ?0? on the toc_ s bit (b4, stat0,...) will set the toc_is bit (b4, ints0,...) t o ?1?. 3 tcklos_ies this bit selects the transition edge of the tcklos_s bit (b3, stat0,...). 0: a transition from ?0? to ?1? on the tcklos_s bit (b3, stat0, ...) will set the tcklos_is bit (b3, ints0,...) to ?1?. (default ) 1: any transition from ?0? to ?1? or from ?1? to ?0? on the tc klos_s bit (b3, stat0,...) will set the tcklos_is bit (b3, ints0, ...) to ?1?. 2 tlos_ies this bit selects the transition edge of the tlos_s bit (b2, stat0,...). 0: a transition from ?0? to ?1? on the tlos_s bit (b2, stat0,...) will set the tlos_is bit (b2, ints0,...) to ?1?. (default) 1: any transition from ?0? to ?1? or from ?1? to ?0? on the tl os_s bit (b2, stat0,...) will set the tlos_is bit (b2, ints0,...) to ?1?. 1 los_ies this bit selects the transition edge of the llos_s bit (b0, stat0,...) and the slos_s bit (b1, stat0,...). 0: a transition from ?0? to ?1? on the llos_s bit (b0, stat0,...) / the slos_s bit (b1, stat0,...) will set the llos_is bit (b0 , ints0,...) / the slos_is bit (b1, ints0,...) to ?1? respectively. (default) 1: any transition from ?0? to ?1? or from ?1? to ?0? on the llo s_s bit (b0, stat0,...) / the slos_s bit (b1, stat0,...) will se t the llos_is bit (b0, ints0,...) / the slos_is bit (b1, ints0,...) to ?1? respectively. 0 ib_ies this bit selects the transition edge of the iba_s bit (b1, stat1,...) and the ibd_s bit (b0, stat1,...). 0: a transition from ?0? to ?1? on the iba_s bit (b1, stat1,...) / the ibd_s bit (b0, stat1,...) will set the iba_is bit (b1, i nts1,...) / the ibd_is bit (b0, ints1,...) to ?1? respectively. (default) 1: any transition from ?0? to ?1? or from ?1? to ?0? on the i ba_s bit (b1, stat1,...) / the ibd_s bit (b0, stat1,...) will set the iba_is bit (b1, ints1,...) / the ibd_is bit (b0, ints1,...) to ?1? respectively. 76543210 - ais_ies pa_ies toc_ies tcklos_ies tlos_ies los_ies ib_ies
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 106 december 7, 2005 intm0 - interrupt mask register 0 address: 01bh, 05bh, 09bh, 0dbh, 11bh, 15bh, 19bh, 1dbh, (ch1~ch8) 21bh, 25bh, 29bh, 2dbh, 31bh, 35bh, 39bh, 3dbh, (ch9~ch16) 41bh, 45bh, 49bh, 4dbh, 51bh, (ch17~ch21) 7dbh (ch0) type: read / write default value: ffh bit name description 7 dac_im this bit is the waveform amplitude overflow interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 6 tja_im this bit is the tja fifo overflow and underflow interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 5 rja_im this bit is the rja fifo overflow and underflow interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 4 toc_im this bit is the line driver toc interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 3 tcklos_im this bit is the tclkn missing interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 2 tlos_im this bit is the tlos interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 1 slos_im this bit is the slos interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 0 llos_im this bit is the llos interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 76543210 dac_im tja_im rja_im toc_im tcklos_im tlos_im slos_im llos_im
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 107 december 7, 2005 intm1 - interrupt mask register 1 address: 01ch, 05ch, 09ch, 0dch, 11ch, 15ch, 19ch, 1dch, (ch1~ch8) 21ch, 25ch, 29ch, 2dch, 31ch, 35ch, 39ch, 3dch, (ch9~ch16) 41ch, 45ch, 49ch, 4dch, 51ch, (ch17~ch21) 7dch (ch0) type: read / write default value: efh bit name description 7 sais_im this bit is the sais interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 6 lais_im this bit is the lais interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 5 pa_im this bit is the prbs/arb pattern synchronization interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 4 - 2 - reserved. 1 iba_im this bit is the activate ib code interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 0 ibd_im this bit is the deactivate ib code interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 76543210 sais_im lais_im pa_im - - - iba_im ibd_im
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 108 december 7, 2005 intm2 - interrupt mask register 2 address: 01dh, 05dh, 09dh, 0ddh, 11dh, 15dh, 19dh, 1ddh, (ch1~ch8) 21dh, 25dh, 29dh, 2ddh, 31dh, 35dh, 39dh, 3ddh, (ch9~ch16) 41dh, 45dh, 49dh, 4ddh, 51dh, (ch17~ch21) 7ddh (ch0) type: read / write default value: 3fh bit name description 7 - 6 - reserved. 5 sbpv_im this bit is the sbpv interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 4 lbpv_im this bit is the lbpv interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 3 sexz_im this bit is the sexz interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 2 lexz_im this bit is the lexz interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 1 err_im this bit is the prbs/arb error interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 0 cntov_im this bit is the errch and errcl registers overflow interrupt mask. 0: interrupt is enabled. 1: interrupt is masked. (default) 76543210 - - sbpv_im lbpv_im sexz_im lexz_im err_im cntov_im
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 109 december 7, 2005 stat0 - status register 0 address: 01eh, 05eh, 09eh, 0deh, 11eh, 15eh, 19eh, 1deh, (ch1~ch8) 21eh, 25eh, 29eh, 2deh, 31eh, 35eh, 39eh, 3deh, (ch9~ch16) 41eh, 45eh, 49eh, 4deh, 51eh, (ch17~ch21) 7deh (ch0) type: read default value: 00h bit name description 7 autolp_s this bit indicates the automatic digital/remote loopback status. 0: out of automatic digital/remote loopback. (default) 1: in automatic digital/remote loopback. 6 - 5 - reserved. 4 toc_s this bit indicates the toc status. 0: no toc is detected. (default) 1: toc is detected. 3 tcklos_s this bit indicates the tclkn missing status. 0: tclkn is not missing. (default) 1: tclkn is missing. 2 tlos_s this bit indicates the tlos status. 0: no tlos is detected. (default) 1: tlos is detected. 1 slos_s this bit indicates the slos status. 0: no slos is detected. (default) 1: slos is detected. 0 llos_s this bit indicates the llos status. 0: no llos is detected. (default) 1: llos is detected. 76543210 autolp_s - - toc_s tcklos_s tlos_s slos_s llos_s
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 110 december 7, 2005 stat1 - status register 1 address: 01fh, 05fh, 09fh, 0dfh, 11fh, 15fh, 19fh, 1dfh, (ch1~ch8) 21fh, 25fh, 29fh, 2dfh, 31fh, 35fh, 39fh, 3dfh, (ch9~ch16) 41fh, 45fh, 49fh, 4dfh, 51fh, (ch17~ch21) 7dfh (ch0) type: read default value: 00h bit name description 7 sais_s this bit indicates the sais status. 0: no sais is detected. (default) 1: sais is detected. 6 lais_s this bit indicates the lais status. 0: no lais is detected. (default) 1: lais is detected. 5 pa_s this bit indicates the prbs/arb pattern synchronization status. 0: the prbs/arb pattern is out of synchronization. (default) 1: the prbs/arb pattern is in synchronization. 4 - 2 - reserved. 1 iba_s this bit indicates the activate ib code status. 0: no activate ib code is detected. (default) 1: activate ib code is detected for more than 40 ms when the autolp bit (b3, loop,...) is ?0? or activate ib code is detected f or more than 5.1 sec. when the autolp bit (b3, loop,...) is ?1?. 0 ibd_s this bit indicates the deactivate ib code status. 0: no deactivate ib code is detected. (default) 1: deactivate ib code is detected for more than 30 ms when the autolp bit (b3, loop,...) is ?0? or deactivate ib code is detected for more than 5.1 sec. when the autolp bit (b3, loop,...) is ?1?. 76543210 sais_s lais_s pa_s - - - iba_s ibd_s
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 111 december 7, 2005 ints0 - interrupt status register 0 address: 020h, 060h, 0a0h, 0e0h, 120h, 160h, 1a0h, 1e0h, (ch1~ch8) 220h, 260h, 2a0h, 2e0h, 320h, 360h, 3a0h, 3e0h, (ch9~ch16) 420h, 460h, 4a0h, 4e0h, 520h, (ch17~ch21) 7e0h (ch0) type: read / write default value: 00h bit name description 7 dac_is this bit indicates the interrupt status of the waveform amplitude overflow. 0: no waveform amplitude overflow interrupt is generated; or a ?1? is written to this bit. (default) 1: waveform amplitude overflow interrupt is generated and is reported by the int pin. 6 tja_is this bit indicates the interrupt status of the tja fifo overflow or underflow. 0: no tja fifo overflow or underflow interrupt is g enerated; or a ?1? is written to this bit. (default) 1: tja fifo overflow or underflow interr upt is generated and is reported by the int pin. 5 rja_is this bit indicates the interrupt status of the rja fifo overflow or underflow. 0: no rja fifo overflow or underflow interrupt is generated; or a ?1? is written to this bit. (default) 1: rja fifo overflow or underflow interrupt is generated and is reported by the int pin. 4 toc_is this bit indicates the interrupt status of the line driver toc. 0: no toc interrupt is generated; or a ?1? is written to this bit. (default) 1: toc interrupt is generated and is reported by the int pin. when the toc_ies bit (b4, intes, ...) is ?0?, a transition from ?0? to ?1? on the toc_s bit (b4, stat0,...) set this bit to ?1?; when th e toc_ies bit (b4, intes,...) is ?1?, any transition (from ?0? to ?1? or from ?1? to ?0?) on the toc_s bit (b4, stat0,...) set this bit to ?1?. 3 tcklos_is this bit indicates the interrupt status of the tclkn missing. 0: no tclkn missing interrupt is generated; or a ?1? is written to this bit. (default) 1: tclkn missing interrupt is generated and is reported by the int pin. when the tcklos_ies bit (b3, intes,...) is ?0?, a transi- tion from ?0? to ?1? on the tcklos_s bit (b3, stat0,...) set this bit to ?1?; when the tcklos_ies bit (b3, intes,...) is ?1?, a ny tran- sition (from ?0? to ?1? or from ?1? to ?0?) on the tcklos_s bit (b3, stat0,...) set this bit to ?1?. 2 tlos_is this bit indicates the interrupt status of tlos. 0: no tlos interrupt is generated; or a ?1? is written to this bit. (default) 1: tlos interrupt is generated and is reported by the int pin. when the tlos_ies bit (b2, int es,...) is ?0?, a transition from ?0? to ?1? on the tlos_s bit (b2, stat0,...) set this bit to ?1?; when the tlos_ies bit (b2, int es,...) is ?1?, any transition (fro m ?0? to ?1? or from ?1? to ?0?) on the tlos_s bit (b2, stat0,...) set this bit to ?1?. 1 slos_is this bit indicates the interrupt status of the slos. 0: no slos interrupt is generated; or a ?1? is written to this bit. (default) 1: slos interrupt is generated and is reported by the int pin. when the los_ies bit (b1, intes ,...) is ?0?, a transition from ?0? to ?1? on the slos_s bit (b1, stat0,...) set this bit to ?1?; w hen the los_ies bit (b1, intes,...) is ?1?, any transition (from ?0 ? to ?1? or from ?1? to ?0?) on the slos_s bit (b1, stat0,...) set this bit to ?1?. 0 llos_is this bit indicates the interrupt status of the llos. 0: no llos interrupt is generated; or a ?1? is written to this bit. (default) 1: llos interrupt is generated and is reported by the int pin. when the los_ies bit (b1, intes,...) is ?0?, a transition from ?0? to ?1? on the llos_s bit (b0, stat0,...) set this bit to ?1?; when the los_ies bit (b1, intes,...) is ?1?, any transition (from ?0 ? to ?1? or from ?1? to ?0?) on the llos_s bit (b0, stat0,...) set this bit to ?1?. 76543210 dac_is tja_is rja_is toc_is tckl os_is tlos_is slos_is llos_is
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 112 december 7, 2005 ints1 - interrupt status register 1 address: 021h, 061h, 0a1h, 0e1h, 121h, 161h, 1a1h, 1e1h, (ch1~ch8) 221h, 261h, 2a1h, 2e1h, 321h, 361h, 3a1h, 3e1h, (ch9~ch16) 421h, 461h, 4a1h, 4e1h, 521h, (ch17~ch21) 7e1h (ch0) type: read / write default value: 00h bit name description 7 sais_is this bit indicates the interrupt status of the sais. 0: no sais interrupt is generated; or a ?1? is written to this bit. (default) 1: sais interrupt is generated and is reported by the int pin. when the ais_ies bit (b6, intes,...) is ?0?, a transition from ?0? to ?1? on the sais_s bit (b7, stat1,...) set this bit to ?1?; when the ais_ies bit (b6, intes,...) is ?1?, any transition (from ?0? to ?1? or from ?1? to ?0?) on the sais_s bit (b7, stat1,...) set this bit to ?1?. 6 lais_is this bit indicates the interrupt status of the lais. 0: no lais interrupt is generated; or a ?1? is written to this bit. (default) 1: lais interrupt is generated and is reported by the int pin. when the ais_ies bit (b6, intes,...) is ?0?, a transition from ?0? to ?1? on the lais_s bit (b6, stat1,...) set this bit to ?1?; when the ais_ies bit (b6, intes,...) is ?1?, any transition (from ?0? to ?1? or from ?1? to ?0?) on the lais_s bit (b6, stat1,...) set this bit to ?1?. 5 pa_is this bit indicates the interrupt status of the prbs/arb pattern synchronization. 0: no prbs/arb pattern synchronization interrupt is generated; or a ?1? is written to this bit. (default) 1: prbs/arb pattern synchronization interrupt is generated and is reported by the int pin. when the pa_ies bit (b5, intes,...) is ?0?, a transition from ?0? to ?1? on the pa_s bit (b5, stat1 ,...) set this bit to ?1?; when the pa_ies bit (b5, intes,...) i s ?1?, any transition (from ?0? to ?1? or from ?1? to ?0?) on the pa_s bit (b5, stat1,...) set this bit to ?1?. 4 - 2 - reserved. 1 iba_is this bit indicates the interrupt status of the activate ib code. 0: no activate ib code interrupt is generated ; or a ?1? is written to this bit. (default) 1: activate ib code interrupt is generated and is reported by the int pin. when the ib_ies bit (b0, intes,...) is ?0?, a transition from ?0? to ?1? on the iba_s bit (b1, stat1,...) set this bit to ?1?; when the ib_ies bit (b0, intes,...) is ?1?, any transitio n (from ?0? to ?1? or from ?1? to ?0?) on the iba_s bit (b1, stat1,...) set this bit to ?1?. 0 ibd_is this bit indicates the interrupt status of the deactivate ib code. 0: no deactivate ib code interrupt is generated; or a ?1? is written to this bit. (default) 1: deactivate ib code interrupt is generated and is reported by the int pin. when the ib_ies bit (b0, intes,...) is ?0?, a transition from ?0? to ?1? on the ibd_s bit (b0, stat1,...) set this bit to ?1?; when the ib_ies bit (b0, intes,...) is ?1?, any transitio n (from ?0? to ?1? or from ?1? to ?0?) on the ibd_s bit (b0, stat1,...) set this bit to ?1?. 76543210 sais_is lais_is pa_is - - - iba_is ibd_is
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 113 december 7, 2005 ints2 - interrupt status register 2 address: 022h, 062h, 0a2h, 0e2h, 122h, 162h, 1a2h, 1e2h, (ch1~ch8) 222h, 262h, 2a2h, 2e2h, 322h, 362h, 3a2h, 3e2h, (ch9~ch16) 422h, 462h, 4a2h, 4e2h, 522h, (ch17~ch21) 7e2h (ch0) type: read / write default value: 00h bit name description 7 - 6 - reserved. 5 sbpv_is this bit indicates the interrupt status of the sbpv. 0: no sbpv interrupt is gene rated; or a ?1? is written to this bit. (default) 1: sbpv interrupt is generated and is reported by the int pin. 4 lbpv_is this bit indicates the in terrupt status of the lbpv. 0: no lbpv interrupt is gen erated; or a ?1? is writte n to this bit. (default) 1: lbpv interrupt is generated and is reported by the int pin. 3 sexz_is this bit indicates the interrupt status of the sexz. 0: no sexz interrupt is generated; or a ?1? is written to this bit. (default) 1: sexz interrupt is genera ted and is re ported by the int pin. 2 lexz_is this bit indicates the interrupt status of the lexz. 0: no lexz interrupt is generated; or a ?1? is written to this bit. (default) 1: lexz interrupt is generated and is reported by the int pin. 1 err_is this bit indicates the interrupt status of the prbs/arb error. 0: no prbs/arb error interrupt is generated; or a ?1? is written to this bit. (default) 1: prbs/arb error interrupt is generated and is reported by the int pin. 0 cntov_is this bit indicates the interrupt status of the errch and errcl registers overflow. 0: no errch or errcl register overflow interrupt is generated; or a ?1? is written to this bit. (default) 1: errch and errcl registers overflow interrupt is generated and is reported by the int pin. 76543210 - - sbpv_is lbpv_is sexz_is lexz_is err_is cntov_is
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 114 december 7, 2005 errcl - error counter low-byte register errch - error counte r high-byte register address: 023h, 063h, 0a3h, 0e3h, 123h, 163h, 1a3h, 1e3h, (ch1~ch8) 223h, 263h, 2a3h, 2e3h, 323h, 363h, 3a3h, 3e3h, (ch9~ch16) 423h, 463h, 4a3h, 4e3h, 523h, (ch17~ch21) 7e3h (ch0) type: read default value: 00h bit name description 7 - 0 errc[7:0] these bits, together with the errc[15:8] bits, refl ect the accumulated error number in the internal error counter . they are updated automatically or manually, as determined by the cnt_md bit (b1, err,...). they should be read in the next round of error counting; otherwise, they will be overwritten. address: 024h, 064h, 0a4h, 0e4h, 124h, 164h, 1a4h, 1e4h, (ch1~ch8) 224h, 264h, 2a4h, 2e4h, 324h, 364h, 3a4h, 3e4h, (ch9~ch16) 424h, 464h, 4a4h, 4e4h, 524h, (ch17~ch21) 7e4h (ch0) type: read default value: 00h bit name description 7 - 0 errc[15:8] (refer to the description of the errcl register.) 76543210 errc7 errc6 errc5 errc4 errc3 errc2 errc1 errc0 76543210 errc15 errc14 errc13 errc12 errc11 errc10 errc9 errc8
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 115 december 7, 2005 jm - jitter measurement config uration for channel 0 register jit_pl - positive peak jitter measurement low-byte register jit_ph - positive peak jitter measurement high-byte register address: 7e5h type: read / write default value: 00h bit name description 7 - 3 - reserved. 2 jm_stop this bit is valid only when the jm_md bit (b1, jm) is ?0?. a transition from ?0? to ?1? on this bit updates the jit_ph, jit_pl and jit_nh, jit_nl registers. this bit must be cleared before the next round. 1 jm_md this bit selects the jitter measurement period. 0: the period is determined manually by setting the jm_stop bit (b2, jm). (default) 1: the period is one second automatically. 0 jm_bw this bit selects the bandwidth of the measured jitter. 0: 20 hz ~ 100 khz. (default) 1: 18 khz ~ 100 khz. address: 7e6h type: read default value: 00h bit name description 7 - 0 jit_p[7:0] these bits, together with the jit_p[11:8] bits, reflect the greatest positive peak value of the demodulated jitt er signal which is measured by channel 0. they are updated automatically or manually, as determined by the jm_md bit (b1, jm). they should be read in the next round of jitter measurement; otherwise, they will be overwritten. the relationship between the greatest positive peak value and the indication in these bits is: positive peak = [jit_ph, jit_pl] / 16 (uipp) address: 7e7h type: read default value: 00h bit name description 7 - 4 - reserved. 3 - 0 jit_p[11:8] (refer to the description of the jit_pl register.) 76543 2 1 0 ---- -jm_stopjm_mdjm_bw 76543210 jit_p7 jit_p6 jit_p5 jit_p4 jit_p3 jit_p2 jit_p1 jit_p0 76543 2 1 0 - - - - jit_p11 jit_p10 jit_p9 jit_p8
idt82p2521 21(+1) channel high-density e1 line interface unit programming information 116 december 7, 2005 jit_nl - negative peak jitter measurement low-byte register jit_nh - negative peak jitter measurement high-byte register address: 7e8h type: read default value: 00h bit name description 7 - 0 jit_n[7:0] these bits, together with the jit_n[11:8] bits, reflect the greatest negative peak value of the demodulated jitt er signal which is measured by channel 0. they are updated automatically or manually, as determined by the jm_md bit (b1, jm). they should be read in the next round of jitter measurement; otherwise, they will be overwritten. the relationship between the greatest negative peak value and the indication in these bits is: negative peak = [jit_nh, jit_nl] / 16 (uipp) address: 7e9h type: read default value: 00h bit name description 7 - 4 - reserved. 3 - 0 jit_n[11:8] (refer to the description of the jit_nl register.) 7654 3 2 1 0 jit_n7 jit_n6 jit_n5 jit_n4 jit_n3 jit_n2 jit_n1 jit_n0 76543 2 1 0 - - - - jit_n11 jit_n10 jit_n9 jit_n8
idt82p2521 21(+1) channel high-density e1 line interface unit jtag 117 december 7, 2005 6jtag the idt82p2521 supports the digita l boundary scan specification as described in the ieee 1149.1 standards. the boundary scan architecture consists of data and instruction registers plus a test access port (tap) controller. the control of the tap is achieved through signals applied to the test mode select (tms) and test clock (tck) input pins. data is shifted into the registers via the test data input (tdi) pin, and shifted out of the registers via the test data output (tdo) pin. both tdi and td o are clocked at a rate determined by tck. the jtag boundary scan registers include bsr (boundary scan register), dir (device identificati on register), br (bypass register) and ir (instruction register). these will be described in the following pages. refer to figure-47 for architecture. figure-47 jtag architecture 6.1 jtag instruction register (ir) the ir with instruction decode block is used to select the test to be executed or the data register to be accessed or both. the instructions include: extest, sample/preload, idcode, bypass, clamp and highz. 6.2 jtag data register 6.2.1 device identification register (idr) the idr can be set to define the version, the part number, the manufacturer identity and a fixed bit. 6.2.2 bypass register (byp) the byp consists of a single bit. it can provide a serial path between the tdi input and the tdo output. bypassing the byr will reduce test access times. 6.2.3 boundary scan register (bsr) the bidirectional ports interface to 2 boundary scan cells: - in cell: the input cell is observable only. - out cell: the output cell is controllable and observable. 6.3 test access port (tap) controller the tap controller is a 16-state synchronous state machine. the states include: test logic reset, run-test/idle, select-dr-scan, capture-dr, shift-dr, exit1-dr, pause-dr, exit2-dr, update-dr, select-ir-scan, capture-ir, shift-ir , exit1-ir, pause-ir, exit2-ir and update-ir. figure-48 shows the state diagram. no te that the figure contains two main branches to access either the data or instruction registers. the value shown next to each state transition in this figure states the value present at tms at each rising edge of tck. bsr (boundary scan register) dir (device identification register) br (bypass register) ir (instruction register) mux tdo tdi tck tms trst control mux select output enable tap (test access port) controller
idt82p2521 21(+1) channel high-density e1 line interface unit jtag 118 december 7, 2005 figure-48 jtag state diagram test-logic reset run test/idle select-dr select-ir capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 0 1 1 1 00 00 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1
idt82p2521 21(+1) channel high-density e1 line interface unit thermal management 119 december 7, 2005 7 thermal management the device is designed to operate over the industry temperature range -40c ~ +85c. to ensure the f unctionality and reliability of the device, the maximum junction temperature, t jmax , should not exceed 125c. in some applications, the dev ice will consume more power and a thermal solution should be provided to ensure the junction temperature t j does not exceed t jmax . below is a table listing thermal data for the idt82p2521. 7.1 junction temperature junction temperature t j is the temperature of package typically at the geographical center of the chip where t he device's electric al circuits are. it can be calculated as follows: equation 1: t j = t a + p * ja where: ja = junction-to-ambient thermal resistance of the package t j = junction temperature t a = ambient temperature p = device power consumption for the idt82p2521, the above values are: ja = 16.7 c/w (when airflow rate is 0 m/s. see the above table ) t jmax = 125 c t a = - 40 c ~ 85 c p = refer to section 8.3 device power consumption and dissipation (typical) 1 7.2 example of junct ion temperature cal- culation assume: t a = 85 c ja = 12.8 c/w (airflow: 1 m/s) p = 1.95 w (e1 120 ? , 100% ones, external impedance matching) the junction temperature t j can be calculated as follows: t j = t a + p * ja = 85 c + 1.95 w x 12.8 c/w = 110.0 c the junction temperature of 110.0 c is below the maximum junction temperature of 125 c, so no ex tra heat enhancement is required. in some operation environments, t he calculated junction temperature might exceed the maximum juncti on temperature of 125 c and an external thermal solution such as a heatsink is required. 7.3 heatsink evaluation a heatsink is expanding the surface area of the device to which it is attached. ja is now a combination of dev ice case and heatsink thermal resistance, as the heat flowing fr om the die junction to ambient goes through the package and the heatsink. ja can be calculated as follows: equation 2: ja = jc + ha where: jc = junction-to-case (heatsink) thermal resistance ha = heatsink-to-ambient thermal resistance for the idt82p2521, jc is 4.90 c/w. ha determines which heatsink can be selected to ensure the junc- tion temperature does not exceed t jmax . according to equation 1 and 2, the heatsink-to-ambient thermal resistance ha can be calculated as follows: equation 3: ha = (t j - t a ) / p - jc assume: t j = 125 c (t jmax ) t a = 85 c p = 3.53 w (e1 75 ? , 100% ones, fully internal impedance matching) jc = 4.90 c/w the heatsink-to-ambient thermal resistance ha can be calculated as follows: ha = (125 c - 85 c ) / 3.53 w - 4.90 c/w = 6.43 c/w that is, if a heatsink whose heatsi nk-to-ambient thermal resistance ha is below or equal to 6.43 c/w is used in such operation environ- ment, the junction temperature will not exceed the maximum junction temperature. package jc (c/w) 1 jb (c/w) 2 ja (c/w) 3 airflow (m/s) 640-pin tepbga 4.90 8.50 16.7 0 12.8 1 11.3 2 10.5 3 10.1 4 9.9 5 note: 1. junction-to-case thermal resistance 2. junction-to-board thermal resistance 3. junction-to-ambient thermal resistance
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 120 december 7, 2005 8 physical and electrical specifications 8.1 absolute maximum ratings symbol parameter min max unit vddd digital core power supply -0.5 2.2 v vdda analog core power supply -0.5 4.6 v vddio i/o power supply -0.5 4.6 v vddt0~21 power supply for transmitter driver -0.5 4.6 v vddr0~21 power supply for receiver -0.5 4.6 v v in input voltage, any digital pin gnd - 0.5 6 v input voltage, any rtip and rring pin 1 gnd - 0.5 vddr + 0.5 v esd voltage, any pin 2 2000 v i in transient latch-up current, any pin 100 ma input current, any digital pin 3 -10 10 ma dc input current, any analog pin 3 100 ma pd maximum power dissipation in package 2.4 4 w t j junction temperature 125 c t s storage temperature -65 +150 c note: 1. reference to ground. 2. human body model. 3. constant input current. 4. if device power consumption exceeds this value, a heat sink must be used. refer to chapter 7 thermal management. caution: exceeding the above values may cause permanent damage. functional operation under these conditions is not implied. exposure to absolute maximum rating conditions for extended period may affect device reliability.
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 121 december 7, 2005 8.2 recommended oper ating conditions symbol parameter min typ. max unit t op operating temperature range -40 85 1 c vddio digital i/o power supply 3.13 3.3 3.47 v vdda analog core power supply 3.13 3.3 3.47 v vddd digital core power supply 1.71 1.8 1.89 v vddt power supply for transmitter driver 3.13 3.3 3.47 v vddr power supply for receiver 3.13 3.3 3.47 v v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 vddio+0.5 v note: 1. an external thermal solution such as heatsink may be requir ed depending on the mode of operation. refer to chapter 7 thermal ma nagement.
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 122 december 7, 2005 8.3 device power consumption and dissipation (typical) 1 mode parameter total consumption (w) total device power dissipation (for thermal consideration, w) per-channel power down saving (mw) 2 1.8 v 3.3 v total fully internal r120in=1 3 partially internal r120in=0 4 external 5 fully internal r120in=1 3 partially internal r120in=0 4 external 5 e1/120 ? prbs 0.23 2.22 2.45 2.45 1.88 1.59 80 60 40 100% ones 0.23 3.00 3.23 3.23 2.40 1.95 130 90 70 e1/75 ? prbs 0.23 2.40 2.62 2.62 2.28 1.64 90 60 50 100% ones 0.23 3.30 3.53 3.53 3.01 2.06 150 120 80 note: 1. test conditions: vddx (t ypical) at 25 c operati ng temperature (ambient). 2. the r_off bit (b5, rcf0,...) and t_off bit (b5, tcf0 ,...) are set to ?1? to enable per-channel power down. 3. the transmitter is in internal impedance matching mode and the rece iver is in fully internal impedance matching mode. that is, the r120in bit (b4, rcf0,...) is set to ?1?. and the t_term[2:0] bits (b2~0, tcf0,.. .) and r_term[2:0] bits (b2~0, rcf0,...) are set according to differ ent cable conditions. 4. the transmitter is in internal impedance matching mode and the receiver is in part ially internal impedance matching mode. that is, the r120in bit (b4, rcf0,. ..) is set to ?0?. and the t_term[2:0] bits (b2~0, tcf0,.. .) and r_term[2:0] bits (b2~0, rcf0,...) are set according to differ ent cable conditions. 5. for e1 mode, both the transmitter and the receiver are in exter nal impedance matching mode. that is, the t_term[2:0] bits (b2~ 0, tcf0,...) are set to ?111? and the r_term[2:0] bits (b2~0, rcf0,...) are set to ?1xx?.
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 123 december 7, 2005 8.4 device power consumption and dissipation (maximum) 1 mode parameter total consumption (w) total device power dissipation (for thermal consideration, w) 1.89 v 3.47 v total fully internal r120in=1 2 partially internal r120in=0 3 external 4 e1/120 ? prbs 0.27 2.39 2.66 2.66 2.09 1.71 100% ones 0.28 3.20 3.48 3.48 2.64 2.07 e1/75 ? prbs 0.27 2.55 2.82 2.82 2.47 1.71 100% ones 0.27 3.50 3.78 3.78 3.26 2.12 note: 1. test conditions: vddx (maximum) at 85 c operating temperature (ambient). 2. the transmitter is in internal impedance matching mode and the rece iver is in fully internal impedance matching mode. that is, the r120in bit (b4, rcf0,...) is set to ?1?. and the t_term[2:0] bits (b2~0, tcf0,.. .) and r_term[2:0] bits (b2~0, rcf0,...) are set according to differ ent cable conditions. 3. the transmitter is in internal impedance matching mode and the receiver is in part ially internal impedance matching mode. that is, the r120in bit (b4, rcf0,. ..) is set to ?0?. and the t_term[2:0] bits (b2~0, tcf0,.. .) and r_term[2:0] bits (b2~0, rcf0,...) are set according to differ ent cable conditions. 4. for e1 mode, both the transmitter and the receiver are in exter nal impedance matching mode. that is, the t_term[2:0] bits (b2~ 0, tcf0,...) are set to ?111? and the r_term[2:0] bits (b2~0, rcf0,...) are set to ?1xx?.
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 124 december 7, 2005 8.5 d.c. characteristics @ ta = -40 to +85 c, vddio = 3.3 v 5%, vddd = 1.8 v 5% symbol parameter min typ. max unit test conditions v ol output low voltage 0.40 v vddio = 3.13 v, i ol = 4 ma, 8 ma v oh output high voltage 2.4 vddio v vddio = 3.13 v, i oh = 4 ma, 8 ma v t+ schmitt trigger input low to high threshold 1.8 v v t- schmitt trigger input high to low threshold 0.7 v r pu internal pull-up /pull-down resistor 50 70 115 k ? i il input low current -1 0 +1 a v il = gndd i ih input high current -1 0 +1 a v ih = vddio c in input digital pin capacitance 10 pf c out output load capacitance 50 pf c out output load capacitance (bus pins) 100 pf i zl leakage current of digital output in high-z mode -10 10 a gndio < v o < vddio z oh output high-z on ttipn, tringn pins 10 k ?
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 125 december 7, 2005 8.6 e1 receiver electr ical characteristics parameter min typ. max unit test conditions receiver sensitivity of receive differen- tial mode with cable loss @ 1024 khz 15 db with nominal pulse amplitude of 3.0 v for 120 ? and 2.37 v for 75 ? termination, adding -18 db interference signal. receiver sensitivity of receive single ended mode with cable loss @ 1024 khz 12 db signal to noise interference margin -14 db @cable loss 0-6 db analog los level (normal mode) alos[2:0] 000 001 (default) 010 011 100 101 110 111 0.5 0.7 0.9 1.2 1.4 1.6 1.8 2.0 v pp in differential mode, measured between rtip and rring pins. in singled ended mode, measured between rtip and gnda pins refer to table-9 for llos criteria declare and clear. los hysteresis 0.25 analog los level (line monitor mode) alos[2:0] 000 001 (default) 010 011 1xx (reserved) 1.0 1.4 1.8 2.2 v pp measured on the line with the monitor gain set by the mg[1:0] bits (b1~0, rcf2,...) equal to the resistive attenuation. refer to table-9 for llos cri- teria declare and clear. los hysteresis 0.41 allowable consecutive zeros before los: g.775 i.431 / etsi300233 32 2048 los reset 12.5 % ones g.775, etsi 300233 receive intrinsic jitter 0.05 u.i. ja disabled; wide band input jitter tolerance: 1 hz ~ 20 hz 20 hz ~ 2.4 khz 18 khz ~ 100 khz 37 5 2 u.i. u.i. u.i. g.823, with 6 db cable attenuation receiver differential input impedance 2.6 k ? @1024 khz; rx port is high-z receiver common mode input imped- ance to gnd 1.6 k ? receiver single ended mode input impedance to gnd 3.1 k ? the rringn pins are open. receive return loss: 51 khz ~ 102 khz 102 khz ~ 2.048 mhz 2.048 mhz ~ 3.072 mhz 12 18 14 db db db g.703 receive path delay: single rail dual rail nrz dual rail rz 6.6 1.8 1.5 u.i. u.i. u.i. ja disabled
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 126 december 7, 2005 8.7 e1 transmitter elec trical characteristics parameter min typ. max unit test conditions output pulse amplitude: e1, 75 ? load e1, 120 ? load 2.14 2.7 2.37 3.0 2.60 3.3 v v differential line inter- face mode zero (space) level: e1, 75 ? load e1, 120 ? load -0.237 -0.3 +0.237 0.3 v v differential line inter- face mode transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses (t1.102) 200 mv output pulse width at 50% of nominal amplitude 232 244 256 ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 ratio of the width of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 transmit analog los level (talos) (differential line interface) talos[1:0] 00 01 (default) 10 11 1.2 0.9 0.6 0.4 v p measured on the ttip and tring pins. talos hysteresis 0.08 transmit analog los level (talos) (single ended line interface) talos[1:0] 00 01 (default) 10 11 0.61 0.48 0.32 0.24 v p measured on the ttip pin. talos hysteresis 0.04 transmit return loss (g.703): 51 khz ~ 102 khz 102 khz ~ 2.048 mhz 2.048 mhz ~ 3.072 mhz 8 14 10 db db db intrinsic transmit jitter 20 hz ~ 100 khz 0.050 u.i. tclk is jitter free transmit path delay: single rail dual rail nrz dual rail rz 8.5 4.5 4.4 u.i. u.i. u.i. ja is disabled line short circuit current 100 map measured on pin
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 127 december 7, 2005 8.8 transmitter and recei ver timing c haracteristics symbol parameter min typ. max unit mclk frequency: e1 2.048 x n (n = 1 ~ 8) mhz mclk tolerance -100 100 ppm mclk duty cycle 30 70 % transmit path tclk frequency: e1 2.048 mhz tclk tolerance -50 +50 ppm tclk duty cycle 10 90 % t1 transmit data setup time 40 ns t2 transmit data hold time 40 ns delay time of oe low to driver high-z 1 s delay time of tclk low to driver high-z tbd s receive path clock recovery capture range 1 : e1 +80 / -80 ppm rclk duty cycle 2 40 50 60 % t4 rclk pulse width 2 : e1 457 488 519 ns t5 rclk pulse width low time: e1 203 244 285 ns t6 rclk pulse width high time: e1 203 244 285 ns rise/fall time 3 20 ns t7 receive data setup time: e1 200 244 ns t8 receive data hold time: e1 200 244 ns note: 1. relative to nominal frequency, mclk = +100 or -100 ppm. 2. rclk duty cycle width will vary depending on extent of the received pulse jitter di splacement. maximum and minimum rclk duty c ycles are for worst case jitter conditions (0.2 ui displacement for e1 per itu g.823). 3. for all digital outputs. c load = 15 pf.
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 128 december 7, 2005 figure-49 transmit clock timing diagram figure-50 receive clock timing diagram tdnn/tmfn tdn/tdpn tclkn t1 t2 t4 t6 t7 t5 t8 t7 t8 rclk rdn/rdpn (rck_es = 0) rdnn/rmfn rdn/rdpn (rck_es = 1) rdnn/rmfn
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 129 december 7, 2005 8.9 clke1 timing characteristics figure-51 clke1 clock timing diagram 8.10 jitter attenuation characteristics symbol parameter min typ. max unit clke1 outputs 2.048 mhz clock t1 clke1 pulse width 488 ns t2 clke1 pulse width high time 232 244 256 ns t3 clke1 pulse width low time 232 244 256 ns t4 llos data setup time 217 244 271 ns t5 llos data hold time 217 244 271 ns clke1 outputs 8khz clock t1 clke1 pulse width 125 s t2 clke1 pulse width high time 62.4 62.5 62.6 s t3 clke1 pulse width low time 62.4 62.5 62.6 s t4 llos data setup time 62.38 62.5 62.62 s t5 llos data hold time 62.38 62.5 62.62 s clke1 t1 t2 t4 t3 t5 llos parameter min typ. max unit jitter transfer function corner (-3 db) frequency: e1, 32/64/128-bit fifo ja_bw = 0 ja_bw = 1 6.63 0.87 hz hz
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 130 december 7, 2005 figure-52 e1 jitter tolerance performance jitter attenuator: e1 (g.736) @ 3 hz @ 40 hz @ 400 hz @ 100 khz -0.5 -0.5 +19.5 +19.5 db db db db jitter attenuator latency delay: 32-bit fifo 64-bit fifo 128-bit fifo 16 32 64 u.i. u.i. u.i. input jitter tolerance before fifo overflow or underflow: 32-bit fifo 64-bit fifo 128-bit fifo 28 56 120 u.i. u.i. u.i. parameter min typ. max unit
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 131 december 7, 2005 figure-53 e1 jitter transfer performance
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 132 december 7, 2005 8.11 microprocessor interface timing 8.11.1 serial micropr ocessor interface a falling transition on cs indicates the start of a read/write operation, and a rising transition indicates the end of the operation. after cs is set to low, a 5-bit instruction on sdi is input to the device on the rising edge of sclk. if the msb is ?1?, it is a read operation. if the msb is ?0?, it is a write operation. following the instruct ion, an 11-bit address is clocked in on sdi to specify the register. if the device is in a read operation, the data read from the specified register is output on sdo on the falling edge of sclk (refer to figure-54). if the device is in a write operation, the data written to the specified r egister is input on sdi following the address byte (refer to figure-55). figure-54 read operation in serial microprocessor interface figure-55 write operation in serial microprocessor interface cs sclk sdi sdo 10 0 1 2 3 4 5 6 7 8 9 11121314151617181920212223 a0 a7 a6 a5 a4 a3 a2 a1 instruction register address high-z d0 d7 d6 d5 d4 d3 d2 d1 don't-care a9 r/w don't care a10 a8 cs sclk sdi sdo 10 0 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23 a0 a7 a6 a5 a4 a3 a2 a1 instruction data byte high-z d0 d7 d6 d5 d4 d3 d2 d1 register address a8 r/w don't care a10 a9
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 133 december 7, 2005 figure-56 timing diagram symbol description min. max. units f op sclk frequency 2.0 mhz t csh minimum cs high time 100 ns t css cs setup time 50 ns t csd cs hold time 100 ns t cld clock disable time 50 ns t clh clock high time 205 ns t cll clock low time 205 ns t dis data setup time 50 ns t dih data hold time 150 ns t pd output delay 150 ns t df output disable time 50 ns cs sclk sdi sdo t csh t css high-z high-z t csd t clh t cll t dis t dih t pd t df valid input valid output t cld
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 134 december 7, 2005 8.11.2 parallel motorola non-mult iplexed microprocessor interface 8.11.2.1read cycle specification figure-57 parallel motorola non-multiplexed microprocessor interface read cycle symbol parameter min max units t sar address to valid read setup time 5 ns t rsw valid read signal width 38 or wait until ack activated ns t har address to valid read hold time 0 ns t rwv r/ w available time after valid cs + ds signal falling edge 0 ns t rwh r/ w hold time after valid cs + ds signal falling edge 33 ns t prd data propagation delay after valid cs + ds signal falling edge 33 ns t zrd valid read negated to output high-z 5 20 ns valid address a[x:0] ds + cs r/ w d[7:0] valid data t sar t har t rwv t rwh t prd t zrd t rsw ack
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 135 december 7, 2005 8.11.2.2write cycle specification figure-58 parallel motorola non-multiplexed microprocessor interface write cycle symbol parameter min max units t saw address to valid write setup time 0 ns t wsw valid write signal width 5 or wait until ack activated ns t haw address to valid write hold time 35 ns t rwv r/ w available time after valid write signal falling edge 0 ns t rwh r/ w hold time after valid write signal falling edge 5 or wait until ack activated ns t dv data available time before valid write signal rising edge 5 ns t dh valid data hold time after valid write signal rising edge 5 ns t rec recovery time from write cycle 5 ns valid address a[x:0] ds + cs r/ w d[7:0] valid data t saw t haw t rwv t rwh t dv t dh t wsw t rec ack
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 136 december 7, 2005 8.11.3 parallel intel non-multip lexed microprocessor interface 8.11.3.1read cycle specification figure-59 parallel intel non-multiplexed microprocessor interface read cycle symbol parameter min max units t sar address to valid read setup time 5 ns t rsw valid read signal width 33 or wait until rdy activated ns t har address to valid read hold time 0 ns t prd data propagation delay after valid read signal falling edge 28 ns t zrd valid read negated to output high-z 5 20 ns valid address a[x:0] rd + cs d[7:0] valid data t sar t har t zrd t rsw t prd note: wr shall be tied to high. rdy
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 137 december 7, 2005 8.11.3.2write cycle specification figure-60 parallel intel non-multiplexed microprocessor interface write cycle symbol parameter min max units t saw address to valid write setup time 0 ns t wsw valid write signal width 5 or wait until rdy activated ns t haw address to valid write hold time 35 ns t dv data available time before valid write signal rising edge 5 ns t dh valid data hold time after valid write signal rising edge 5 ns t rec recovery time from write cycle 5 ns valid address a[x:0] wr + cs d[7:0] valid data t saw t haw t dv t dh note: rd shall be tied to high. rdy t wsw t rec
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 138 december 7, 2005 8.11.4 parallel motorola multip lexed microprocessor interface 8.11.4.1read cycle specification figure-61 parallel motorola multiplexed microprocessor interface read cycle symbol parameter min max units t asw valid as signal width 5 ns t rsw valid read signal width 38 or wait until ack activated ns t csd valid ds + cs falling edge delay after as 0 ns t rwv r/ w available time after valid ds + cs signal falling edge 0 ns t rwh r/ w hold time after valid ds + cs signal falling edge 33 ns t vas valid address to as setup time 5 ns t vah valid address to as hold time 5 ns t prd data propagation delay after valid ds + cs signal falling edge 33 ns t zrd valid read negated to output high-z before valid as rising edge 520ns ds + cs r/ w d[7:0] valid data t rwv t rwh t prd t zrd t rsw ack as valid address t asw t csd t vas t vah
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 139 december 7, 2005 8.11.4.2write cycle specification figure-62 parallel moto rola multiplexed microproc essor interface write cycle symbol parameter min max units t asw valid as signal width 5 ns t wsw valid write signal width 5 or wait until ack acti- vated ns t hcw ds + cs to valid hold time 35 ns t rwv r/ w available time after valid write signal falling edge 0 ns t rwh r/ w hold time after valid write signal falling edge 5 ns t csd valid ds + cs falling edge delay after as 0 ns t vas valid address to as setup time 5 ns t vah valid address to as hold time 5 ns t asd valid as rising edge delay after ds + cs rising edge 5 ns t dv data available time before valid write signal rising edge 5 ns t dh valid data hold time after valid write signal rising edge before the next as rising edge 5ns ds + cs r/ w d[7:0] valid data t rwv t rwh t dv t dh t wsw ack as t asw t csd valid address t vas t vah t hcw t asd
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 140 december 7, 2005 8.11.5 parallel intel multipl exed microprocessor interface 8.11.5.1read cycle specification figure-63 parallel inte l multiplexed microprocessor interface read cycle symbol parameter min max units t aew valid ale signal width 5 ns t rsw valid read signal width 33 or wait until rdy activated ns t csd valid rd + cs falling edge delay after ale falling edge 0 ns t vas valid address to ale setup time 5 ns t vah valid address to ale hold time 5 ns t prd data propagation delay after valid read signal falling edge 28 ns t zrd valid read negated to output high-z before valid ale rising edge 5 20 ns rd + cs d[7:0] valid data t zrd t rsw t prd note: wr shall be tied to high. rdy t aew t csd ale valid address t vas t vah
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 141 december 7, 2005 8.11.5.2write cycle specification figure-64 parallel intel multiplexed microprocessor interface write cycle symbol parameter min max units t aew valid ale signal width 5 ns t wsw valid write signal width 5 or wait until rdy acti- vated ns t hcw wr + cs to valid hold time 35 ns t csd valid wr + cs falling edge delay after ale falling edge 0 ns t vas valid address to ale setup time 5 ns t vah valid address to ale hold time 5 ns t aed valid ale rising edge delay after wr + cs rising edge 5 ns t dv data available time before valid write signal rising edge 5 ns t dh valid data hold time after valid write signal rising edge before the next as rising edge 5 ns wr + cs d[7:0] note: rd shall be tied to high. rdy t wsw t hcw t aew t csd t aed ale valid data t dv t dh valid address t vas t vah
idt82p2521 21(+1) channel high-density e1 line interface unit physical and electrical speci fications 142 december 7, 2005 8.12 jtag timing characteristics figure-65 jtag timing symbol parameter min typ. max unit t1 tck period 100 ns t2 tms to tck setup time; tdi to tck setup time 25 ns t3 tck to tms hold time; tck to tdi hold time 25 ns t4 tck to tdo delay time 50 ns t1 t2 t3 t4 tck tms tdi tdo
glossary 143 december 7, 2005 ais ? alarm indication signal ami ? alternate mark inversion arb ? arbitrary pattern bpv ? bipolar violation cf ? corner frequency cv ? code violation dpll ? digital phase locked loop exz ? excessive zeroes fifo ? first in first out hdb3 ? high density bipolar 3 hps ? hitless protection switching ib ? inband loopback lais ? line alarm indication signal lbpv ? line bipolar violation lexz ? line excessive zeroes llos ? line loss of signal los ? loss of signal nrz ? non-return to zero pbx ? private branch exchange prbs ? pseudo random bit sequence qrss ? quasi-random signal source rja ? receive jitter attenuator rz ? return to zero sais ? system alarm indication signal sbpv ? system bipolar violation sdh ? synchronous digital hierarchy sexz ? system excessive zeroes glossary
idt82p2521 21(+1) channel high-density e1 line interface unit glossary 144 december 7, 2005 slos ?system los sonet ? synchronous optical network tepbga ? thermally enhanced plastic ball grid array tja ? transmit jitter attenuator tlos ? transmit loss of signal toc ? transmit over current
index 145 december 7, 2005 a alarm indication signal (ais) ............................................................. 46 b bipolar violation (bpv) ....................................................................... 42 c cable coaxial cable ........................................................... 29 , 31 , 38 , 39 twisted pair cable ................................................................. 29 , 38 clock input mclk ......................................................................................... 65 xclk .......................................................................................... 65 clock output clke1 ........................................................................................ 60 refa/refb ............................................................................... 61 clka/clkb .......................................................................... 61 mclk ................................................................................... 61 recovery clock ....................................................................... 61 code violation (cv) ............................................................................ 42 common control .................................................................................. 23 corner frequency (cf) ...................................................................... 41 d decoder .............................................................................................. 33 e encoder .............................................................................................. 35 error counter ....................................................................................... 49 excessive zeroes (exz) ..................................................................... 42 f free running ................................................................................. 60 , 61 g g.772 monitoring ................................................................................ 58 h heatsink ............................................................................................ 119 high impedance ........................................................18 , 29 , 34 , 38 , 40 hitless protection switch (hps) ......................................................... 29 hitless switch ...................................................................................... 29 hot-swap ............................................................................................ 29 hot-switchover .................................................................................... 29 i impedance matching receive external impedance matching ..........................................29 , 31 fully internal impedance matching .......................................... 29 partially internal impedance matching ..................................... 29 transmit external impedance matching ................................................ 38 internal impedance matching ...........................................38 , 39 interrupt .............................................................................................. 66 j ja-limit .............................................................................................. 41 jitter measurement (jm) .................................................................... 59 jtag ..........................................................................................26 , 117 l line interface .......................................................................... 18 , 29 , 38 receive differential ............................................................................ 29 single ended ........................................................................ 31 transmit differential ............................................................................ 38 single ended ........................................................................ 39 line monitor ........................................................................................ 32 loopback analog loopback ....................................................................... 53 digital loopback ........................................................................ 55 dual loopback manual remote loopback + automatic digital loopback ........... 56 manual remote loopback + manual digital loopback .............. 56 remote loopback ...................................................................... 54 loss of signal (los) .......................................................................... 43 line los (llos) ....................................................................... 43 system los (slos) .................................................................. 44 transmit los (tlos) ................................................................ 45 m microprocessor interface ..............................................................24 , 69 monitoring index
idt82p2521 21(+1) channel high-density e1 line interface unit index 146 december 7, 2005 g.772 monitoring ........................................................................ 58 line monitor ................................................................................. 32 p pattern arb ..................................................................................... 47 , 48 inband loopback (ib) .......................................................... 47 , 49 prbs ................................................................................... 47 , 48 power down ................................................................................. 34 , 40 receiver ....................................................................................... 34 transmitter ................................................................................... 40 protected non-intrusive monitoring .................................................... 32 r receive sensitivity ............................................................................... 32 reset global software reset .................................................................. 69 hardware reset ............................................................................ 69 power-on reset ............................................................................ 69 rx clock & data recovery ................................................................... 33 s slicer ................................................................................................... 33 system interface .................................................................... 19 , 33 , 34 receive dual rail nrz format ........................................................... 33 dual rail rz format .............................................................. 33 dual rail sliced .................................................................... 33 single rail nrz format ......................................................... 33 transmit dual rail nrz format ........................................................... 34 dual rail rz format .............................................................. 34 single rail nrz format ......................................................... 34 t transmit over current (toc) ......................................................38 , 52 w waveform template ............................................................................. 35
idt82p2816 high-density t1/e 1/j1 line interface unit idt82p2521 21(+1) channel high-density e1 line interface unit 147 idt and the idt logo are trademarks of integrated device technology, inc. corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: 408-360-1552 email:telecomhelp@idt.com ordering information idt xxxxxxx xx x device type package process/temperature range blank industrial (-40 c to +85 c) bh thermally enhanced plastic ball grid array (640-pin tepbga, bh640) bhg green thermally enhanced plastic ball grid array (640-pin tepbga, bhg640) 82p2521 21(+1) high-density e1 line interface unit data sheet document history 12/07/2005 pages 10, 20, 23, 43, 70, 71, 72, 119, 120, 125, 132

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